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Cover Article

Functional Verification for Agile Processor Development: A Case for Workflow Integration

State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
University of Chinese Academy of Sciences, Beijing 100049, China
Beijing Institute of Open Source Chip, Beijing 100080, China
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Abstract

Agile hardware development methodology has been widely adopted over the past decade. Despite the research progress, the industry still doubts its applicability, especially for the functional verification of complicated processor chips. Functional verification commonly employs a simulation-based method of co-simulating the design under test with a reference model and checking the consistency of their outcomes given the same input stimuli. We observe limited collaboration and information exchange through the design and verification processes, dramatically leading to inefficiencies when applying the conventional functional verification workflow to agile development. In this paper, we propose workflow integration with collaborative task delegation and dynamic information exchange as the design principles to effectively address the challenges on functional verification under the agile development model. Based on workflow integration, we enhance the functional verification workflows with a series of novel methodologies and toolchains. The diff-rule based agile verification methodology (DRAV) reduces the overhead of building reference models with runtime execution information from designs under test. We present the RISC-V implementation for DRAV, DiffTest, which adopts information probes to extract internal design behaviors for co-simulation and debugging. It further integrates two plugins, namely XFUZZ for effective test generation guided by design coverage metrics and LightSSS for efficient fault analysis triggered by co-simulation mismatches. We present the integrated workflows for agile hardware development and demonstrate their effectiveness in designing and verifying RISC-V processors with 33 functional bugs found in NutShell. We also illustrate the efficiency of the proposed toolchains with a case study on a functional bug in the L2 cache of XiangShan.

Keywords

functional verificationagile developmentopen-source hardwareworkflow integration

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Journal of Computer Science and Technology
Volume 38 Issue 4,
July 2023
Pages 737-753
DOI: 10.1007/s11390-023-3285-8
Cite this article:
Xu Y-N, Yu Z-H, Wang K-F, et al. Functional Verification for Agile Processor Development: A Case for Workflow Integration. Journal of Computer Science and Technology, 2023, 38(4): 737-753. https://doi.org/10.1007/s11390-023-3285-8

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Received: 07 April 2023
Accepted: 05 July 2023
Published: 06 December 2023
© Institute of Computing Technology, Chinese Academy of Sciences 2023
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