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Research Article

Ultimate dielectric scaling of 2D transistors via van der Waals metal integration

Weiqi Dang1, Bei Zhao1, Chang Liu3, Xiangdong Yang1, Lingan Kong2, Zheyi Lu2, Bo Li1,2, Jia Li1, Hongmei Zhang1, Wanying Li2, Shun Shi2, Ziyue Qin1, Lei Liao3, Xidong Duan1( ), Yuan Liu2 ( )
Hunan Key Laboratory of Two-Dimensional Materials and State Key Laboratory for Chemo/Biosensing and Chemometrics, College of Chemistry and Chemical Engineering Hunan UniversityChangsha 410082 China
Hunan Key Laboratory of Two-Dimensional Materials, Department of Applied Physics, School of Physics and Electronics Hunan UniversityChangsha 410082 China
Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education & Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices, School of Physics and Electronics Hunan UniversityChangsha 410082 China
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Abstract

The two-dimensional transition metal dichalcogenides (TMDs) have attracted intense interest as an atomically thin semiconductor channel for the continued transistor scaling. However, with a dangling bond free surface, it has been a key challenge to reliably integrate high-quality gate dielectrics on TMDs. In particular, the atomic layer deposition of dielectrics on TMDs typically features highly non-uniform nucleation and produces a highly rough or porous dielectric film with rich pinholes that are prone to further damage during the gate integration process. Herein we report a van der Waals (vdW) integration route towards highly reliable gate metal integration on porous dielectrics. The physical lamination process employed by the vdW integration avoids the direct deposition of metal electrodes into porous dielectrics to ensure reliable gate integration and produce low gate leakage devices. The electrical measurements demonstrate the vdW integrated MoS2 top gate devices exhibit substantially reduced gate leakage current that is about 3–5 orders of magnitude smaller than that with deposited metal electrodes. Furthermore, we show the vdW integration process can be used to create high performance top-gated MoS2 transistors with ultrathin Al2O3 dielectrics down to 1 nm, representing the ultimate dielectric scaling for TMDs transistors. This study demonstrates that vdW integration can enable highly reliable gate integration on relatively low quality dielectrics on TMDs, and opens an interesting pathway to high-performance top-gate transistors using dangling bond free two-dimensional (2D) semiconductors.

Keywords

van der Waals (vdW) integrationdielectric scalingtransfer gateMoS2metal oxide semiconductor field effect transistor (MOSFET)

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Nano Research
Volume 15 Issue 2,
February 2022
Pages 1603-1608
DOI: 10.1007/s12274-021-3708-1
Cite this article:
Dang W, Zhao B, Liu C, et al. Ultimate dielectric scaling of 2D transistors via van der Waals metal integration. Nano Research, 2022, 15(2): 1603-1608. https://doi.org/10.1007/s12274-021-3708-1
Topics:
Field effect transistors

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Received: 02 April 2021
Revised: 09 June 2021
Accepted: 22 June 2021
Published: 05 August 2021
© Tsinghua University Press and Springer-Verlag GmbH Germany, part of Springer Nature 2021
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