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Research Article

Wafer-scale carbon-based CMOS PDK compatible with silicon-based VLSI design flow

Minghui Yin1,2,3, Haitao Xu4,5( ), Yunxia You1,3, Ningfei Gao4, Weihua Zhang1,2,3, Hongwei Liu1,2,3, Huanhuan Zhou1,3, Chen Wang1,3, Lian-Mao Peng6, Zhiqiang Li1,2,3( )
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
University of Chinese Academy of Sciences, Beijing 100049, China
State Key Lab of Fabrication Technologies for Integrated Circuits, Beijing 100029, China
Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd., Beijing 101399, China
Institute of Carbon-based Thin Film Electronics, Peking University, Shanxi 030012, China
Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China
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Graphical Abstract

A set of wafer-scale carbon-based metal-oxide-semiconductor (CMOS) process design kit (PDK) compatible with silicon-based very-large-scale integration (VLSI) design flow is designed and validated. Evaluation of the performance–power–area (PPA) electrical characteristics and design of static random-access memory (SRAM) circuit system based on carbon-based process are completed.

Abstract

Carbon nanotube field-effect transistors (CNTFETs) are increasingly recognized as a viable option for creating high-performance, low-power, and densely integrated circuits (ICs). Advancements in carbon-based electronics, encompassing materials and device technology, have enabled the fabrication of circuits with over 1000 gates, marking carbon-based integrated circuit design as a burgeoning field of research. A critical challenge in the realm of carbon-based very-large-scale integration (VLSI) is the lack of suitable automated design methodologies and infrastructure platforms. In this study, we present the development of a wafer-scale 3 µm carbon-based complementary metal-oxide-semiconductor (CMOS) process design kit (PDK) (3 µm-CNTFETs-PDK) compatible with silicon-based Electronic Design Automation (EDA) tools and VLSI circuit design flow. The proposed 3 µm-CNTFETs-PDK features a contacted gate pitch (CGP) of 21 µm, a gate density of 128 gates/mm², and a transistor density of 554 transistors/mm², with an intrinsic gate delay around 134 ns. Validation of the 3 µm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits. Leveraging the carbon-based PDK and a silicon-based design platform, we successfully implemented a complete 64-bit static random-access memory (SRAM) circuit system for the first time, which exhibited timing, power, and area characteristics of clock@10 kHz, 122.1 µW, 3795 µm × 2810 µm. This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow, thereby laying the groundwork for future carbon-based VLSI advancements.

Keywords

carbon nanotube field-effect transistors (CNTFETs)complementary metal-oxide-semiconductor (CMOS)process design kit (PDK)wafer-scalevery-large-scale integration (VLSI)

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Nano Research
Volume 17 Issue 8,
August 2024
Pages 7557-7566
DOI: 10.1007/s12274-024-6583-8
Cite this article:
Yin M, Xu H, You Y, et al. Wafer-scale carbon-based CMOS PDK compatible with silicon-based VLSI design flow. Nano Research, 2024, 17(8): 7557-7566. https://doi.org/10.1007/s12274-024-6583-8
Topics:
CMOS integrated circuitsNanoelectronics Semiconductor devices ULSI circuits

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Received: 04 January 2024
Revised: 07 February 2024
Accepted: 22 February 2024
Published: 24 June 2024
© Tsinghua University Press 2024
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