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Open Access

Design of Low-Power Modern Radar SoC Based on ASIX

Bing Yang, Zongguang Yu( ), Jinghe Wei
Schoolol of Internet of Things Engineering, Jiangnan University, Wuxi 214122, China
China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China
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Abstract

With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip (SoC) based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18- μm 1P6M Salicide CMOS process, the area is 7.825 mm × 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.

Keywords

ASIX coreSystem on a Chip (SoC)low powersystem levelcircuit levellogic levelphysical levelmodern radar

References

[1]
C.-H. Jan, M. Agostinelli, and M. Buehler, A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance and high density product applications, in Proc. of Electron Devices Meeting (IEDM), 2009 IEEE International, Baltimore, MD, USA, 2009, pp. 569-575.
[2]
C. J. Lin, S. H. Kang, and Y. J. Wang, 45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell, in Proc. of Electron Devices Meeting (IEDM), 2009 IEEE International, Baltimore, MD, USA, 2009, pp. 767-772.
Crossref
[3]
C. Wang, C. Huang, C. Lee, and T. Cheng, A low power high-speed 8-bit pipelining CLA design using dual-threshold voltage domino logic, Very Large Scale Integration (VLSI) Systems, IEEE Transactions ,vol. 16, no. 5, pp. 594-598, 2008.
Crossref Google Scholar
[4]
Y. Li, R. Huang, and Y. Cai, A novel dual-doping floating-gate (DDFG) Flash memory featuring low power and high reliability application, Electron Device Letters, IEEE Transactions, vol. 28, no. 7, pp. 622-624, 2007.
Crossref Google Scholar
[5]
B. Schelland Y. Tsividis, A low power tunable delay element suitable for asynchronous delays of burst information, Solid-State Circuits, IEEE Journal ,vol. 43, no. 5, pp. 1227-1234, 2008.
Crossref Google Scholar
[6]
Z. Guo, L. Wu, Y. Liu, and Q. Zhang, A novel embedded soft-start circuit for SOC power supply, (in Chinese), Journal of Semiconductors, vol. 31, no. 5, pp. 133-138, 2010.
Crossref Google Scholar
[7]
Y. Zhang, Z. Chen, and W. Lu, A fully integrated CMOS readout circuit for particle detectors, (in Chinese), Journal of Semiconductor, vol. 28, no. 2, pp. 182-188, 2007.
Google Scholar
[8]
T. Sasao, Easily testable realizations for generalized Reed-Muller expressions, Transactions on Computers, vol. 46, no. 6, p. 709, 1997.
Crossref Google Scholar
[9]
P. Wang, J. Lu, and K. Chen, Low power polarity conversion based on the whole annealing genetic algorithm, Journal of Semi-conductors, vol. 29, no. 2, p. 298, 2008.
Google Scholar
[10]
Al. B. A. Jassani, N. Urquhart, and A. E. A. Almaini, Manipulation and optimisation techniques for Boolean logic, Computers and Digital Techniques, vol. 4, no. 3, p. 227, 2010.
Crossref Google Scholar
[11]
D. Song, Y. Ren, and Z. Yao, The design of a low-power underwater multi channel real-time acquisition and storage device, Journal of Electron Devices ,vol. 36, no. 4, pp. 502-505, 2013.
Google Scholar
[12]
R. Zhou, T. Mo, and Y. Gan, Ultra-low power analog front End of wake-up receiver for 5.8 GHz ETC, Semiconductor Technology ,vol. 38, no. 7, pp. 487-491, 496, 2013.
Google Scholar
[13]
X. Zhang, G. Du, and Y. Wang, Ultra-low-power integrated circuit technology, Scientia Sinica Informationis ,vol. 42, no. 12, pp. 544-1558, 2012.
Crossref Google Scholar
[14]
N. Xiand S. Xu, A design method of low power consumption much core system processing unit of automation, Manufacturing Automation ,vol. 34, no. 18, pp. 128-130, 2012.
Google Scholar
[15]
T. Zhouand H. Xiong, Sign of energy-efficient hierarchical scheduling for integrated modular avionics systems, Chinese Journal of Aeronautics, vol. 25, no. 1, pp. 109-114, 2012.
Crossref Google Scholar
[16]
H. Tao, J. Hou, and Z. Shao, Novel operation mechanism of capacitorless DRAM cell using impact ionization and GIDL effects, Computer Technology and Application ,vol. 4, no. 7, pp. 351-355, 2013.
Google Scholar
[17]
H. Zhang, G. Wang, and M. Lu, ASIC design of a low-power high-integration MP3 decoder IP, (in Chinese), Journal of Chongqing University of Posts and Telecommunications, vol. 25, no. 4, pp. 494-499, 2013.
Google Scholar
Tsinghua Science and Technology
Volume 19 Issue 2,
April 2014
Pages 168-173
DOI: 10.1109/TST.2014.6787370
Cite this article:
Yang B, Yu Z, Wei J. Design of Low-Power Modern Radar SoC Based on ASIX. Tsinghua Science and Technology, 2014, 19(2): 168-173. https://doi.org/10.1109/TST.2014.6787370

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Received: 18 February 2014
Revised: 24 February 2014
Accepted: 04 March 2014
Published: 15 April 2014
© The author(s) 2014
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