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Open Access

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

Zongguang Yu, Xiaobo Su, Zhenhai Chen( ), Jiaxuan Zou, Jinghe Wei, Hong Zhang, Yan Xue
Department of Microelectronics, Xidian University, Xi’an 710071, China.
No. 58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China.
School of Electronics and Information Engineering, Xi’an Jiaotong University, Xi’an 710049, China.
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Abstract

A feed-forward Common-Mode (CM) charge control circuit for a high-speed Charge-Domain (CD) pipelined Analog-to-Digital Converter (ADC) is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18- μm CMOS process. The ADC achieved a Spurious Free Dynamic Range (SFDR) of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0–1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm 2.

Keywords

low powerpipelined analog-to-digital convertercharge domainfeed-forward control

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Tsinghua Science and Technology
Volume 23 Issue 1,
February 2018
Pages 87-94
DOI: 10.26599/TST.2018.9010030
Cite this article:
Yu Z, Su X, Chen Z, et al. A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control. Tsinghua Science and Technology, 2018, 23(1): 87-94. https://doi.org/10.26599/TST.2018.9010030

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Received: 29 December 2016
Accepted: 24 May 2017
Published: 15 February 2018
© The authors 2018
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