[1]
Q. X. Zhao, L. Xu, Y. M. Mao, S. P. Leng, G. Y. Min, J. Hu, and N. Najjari, Service-oriented wireless multimedia multicasting with partial frequency reuse, Tsinghua Science and Technology, vol. 21, no. 6, pp. 598-609, 2016.
[2]
A. M. A. Ali, H. Dinc, P. Bhoraskar, C. Dillon, S. Puckett, B. Gray, C. Speir, J. Lanford, J. Brusilius, P. R. Derounian, et. al., A 14-b 1 GS/s RF sampling pipelined ADC with background calibration, IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2857-2867, 2014.
[3]
M. El-Chammas, X. P. Li, S. Kimura, J. Coulon, J. Hu, D. Smith, P. Landman, and M. Weaver, A 90 dB SFDR 14-b 500 MS/s BiCMOS switched-current pipelined ADC, presented at the 2015 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2015.
[4]
W. T. Li, F. L. Li, C. Y. Yang, S.J. Li, and Z. H. Wang, An 85 mW 14-bit 150 MS/s pipelined ADC with a merged first and second MDAC, China Communications, vol. 12, no. 5, pp. 14-22, 2015.
[5]
S. Yi, S. B. Liu, and Z. M. Zhu. A 10-b 50-MS/s two-stage pipelined SAR ADC in 180 nm CMOS, Journal of Semiconductors, vol. 37, no. 6, p. 065001-6, 2013.
[6]
V. Tripathi and B. Murmann, A 160 MS/s, 11.1 mW, single- channel pipelined SAR ADC with 68.3 dB SNDR, presented at the 2014 IEEE Proceedings of the Custom Integrated Circuits Conference, San Jose, CA, USA, 2014.
[7]
L. Brooks and H. S. Lee, A 12-b 50-MS/s fully differential zero-crossing-based ADC without CMFB, presented at the 2009 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2009.
[8]
J. Hu, N. Dolev, and B. Murmann, A 9.4-bit 50-MS/s, 1.44 mW pipelined ADC using dynamic source follower residue amplification, IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1057-1066, 2009.
[9]
H. H. Boo, D. S. Boning, and H. S. Lee, A 12-b 250 MS/s pipelined ADC with virtual ground reference buffers, IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2912-2921, 2015.
[10]
M. Anthony, E. Kohler, J. Kurtze, L. Kushner, and G. Sollner, A process-scalable low-power charge-domain 13-bit pipeline ADC, presented at the 2008 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2008.
[11]
Z. H. Chen, Z. G. Yu, S. R. Huang, H. Zhang, and H. C. Ji, A PVT Insensitive boosted charge transfer for high speed charge-domain pipelined ADCs, IEICE Electronics Express, vol. 9, no. 6, pp. 565-571, 2012.
[12]
Z. H. Chen, S. R. Huang, H. Zhang, and H. C. Ji, A 27-mW 10-bit 125-MSPS charge-domain pipelined ADC with PVT insensitive boosted charge transfer, Journal of Semiconductors, vol. 34, no. 3, p. 035009-9, 2013.
[13]
Z. H. Chen, H. W. Qian, S. R. Huang, H. Zhang, and Z. G. Yu, Low power time-interleaved 10-bit 250MS/s charge domain pipelined ADC for IF sampling, Journal of Semiconductors, vol. 34, no. 6, p. 065005-8, 2013.
[14]
S. R. Huang, H. Zhang, Z. H. Chen, S. Zhu, Z. G. Yu, H. W. Qian, and Y. Hao, A 10-bit 250MS/s charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit, Journal of Semiconductors, vol. 36, no. 5, p. 055012-7, 2015.
[15]
B. Peng; G. Z. Huang, H. Li, P. Y. Wan, and P. F. Lin, A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS, presented at the 2011 IEEE Proceedings of the Custom Integrated Circuits Conference, San Jose, CA, USA, 2011.
[16]
X. Wang, C. Y. Yang, X. X. Zhao, C. Wu, Z. H. Wang, and B. Wu, A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end, presented at the 2012 IEEE International Symposium on Circuits and Systems, Seoul, South Korea, 2012.
[17]
S. K. Shin, J. C. Rudell, D. C. Daly, C. Z. Munoz, D.Y. Chang, K. Gulati, H.S. Lee, and M.Z. Straayer, A 12-bit, 200MS/s zero-crossing based pipelined ADC with early sub-ADC decision and output residue background calibration, IEEE Journal of Solid-State Circuits, vol. 49, no. 6, pp. 1366-1382, 2014.
[18]
A. Nazari, E. Mikkola, B. Jalali, and H. Barnaby, A 12-b, 650-MSps time-interleaved pipeline analog to digital converter with 1.5 GHz analog bandwidth for digital beam-forming systems, Analog Integrated Circuits & Signal Processing, vol. 89, no. 8, pp. 213-222, 2016.