AI Chat Paper
Note: Please note that the following content is generated by AMiner AI. SciOpen does not take any responsibility related to this content.
{{lang === 'zh_CN' ? '文章概述' : 'Summary'}}
{{lang === 'en_US' ? '中' : 'Eng'}}
Chat more with AI
Powered by AMiner. Clicking this button will take you away from SciOpen.
Home Tsinghua Science and Technology Article
PDF (11.4 MB)
Cite
EndNote(RIS) BibTeX
Collect
Submit Manuscript AI Chat Paper
Show Outline
Outline
Show full outline
Hide outline
Outline
Show full outline
Hide outline
Open Access

Review of Technologies for High-Voltage Integrated Circuits

State Key Laboratory of Electronic Thin Films and Integrated Devices, and School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China
Show Author Information

Abstract

High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors’ group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

Keywords

High-Voltage ICs (HVICs)high-voltage integrated technologyBipolar-CMOS-DMOS (BCD) processintegrated power semiconductor devicessuperjunction

References

[1]
C. M. Hu, Optimum doping profile for minimum ohmic resistance and high-breakdown voltage, IEEE Trans. Electron Dev., vol. 26, no. 3, pp. 243-244, 1979.
Crossref Google Scholar
[2]
B. J. Baliga, The IGBT Device: Physics, Design and Applications of the Insulated Gate Bipolar Transistor. Amsterdam, the Netherlands: Elsevier, 2015.
[3]
D. J. Coe, High voltage semiconductor device, U.S. Patent US4754310, June 28, 1988.
[4]
X. B. Chen, Semiconductor power devices with alternating conductivity type high-voltage breakdown regions, U.S. Patent US5216275, June 01, 1993.
[5]
J. Tihanyi, Power MOSFET, U.S. Patent US5438215, August 01, 1995.
[6]
X. B. Chen and J. K. O. Sin, Optimization of the specific on-resistance of the COOLMOSTM, IEEE Trans. Electron Dev., vol. 48, no. 2, pp. 344-348, 2001.
Crossref Google Scholar
[7]
W. T. Zhang, B. Zhang, M. Qiao, Z. H. Li, X. R. Luo, and Z. J. Li, The RON,min of balanced symmetric vertical super junction based on R-well model, IEEE Trans. Electron Dev., vol. 64, no. 1, pp. 224-230, 2017.
Crossref Google Scholar
[8]
D. Disney, I. L. Y. Park, W. C. Lin, and J. Kim, High-voltage IC technologies for AC/DC power conversion, in Proc. of IEEE Int. Conf. Electron Devices and Solid-State Circuits, Singapore, 2015, pp. 142-145.
Crossref
[9]
A. Pressman, K. Billings, and T. Morey, Switching Power Supply Design. 3rd ed. New York, NY, USA: McGraw-Hill Education, 2009.
[10]
S. Krishna, J. Kuo, and I. S. Gaeta, An analog technology integrates bipolar, CMOS, and high-voltage DMOS transistors, IEEE Trans. Electron Dev., vol. 31, no. 1, pp. 89-95, 1984.
Crossref Google Scholar
[11]
A. Andreini, C. Contiero, and P. Galbiati, A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts, IEEE Trans. Electron Dev., vol. 33, no. 12, pp. 2025-2030, 1986.
Crossref Google Scholar
[12]
K. Mao, M. Qiao, L. L. Jiang, H. P. Jiang, Z. H. Li, W. Z. Chen, Z. J. Li, and B. Zhang, A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS, in Proc. of 2013 25th Int. Symp. Power Semiconductor Devices & IC’s, Kanazawa, Japan, 2013, pp. 397-400.
[13]
A. W. Ludikhuize, A versatile 700-1200-V IC process for analog and switching applications, IEEE Trans. Electron Dev., vol. 38, no. 7, pp. 1582-1589, 1991.
Crossref Google Scholar
[14]
M. Qiao, X. D. Zhou, X. Zheng, J. Fang, B. Zhang, and Z. J. Li, A versatile 600 V BCD process for high voltage applications, in Proc. of Int. Conf. Communications, Circuits and Systems, Kokura, Japan, 2007, pp. 1248-1251.
[15]
M. Venturato, G. Cantone, F. Ronchi, and F. Toia, A novel 0.35μm 800V BCD technology platform for offline applications, in Proc. of 24th Int. Symp. Power Semiconductor Devices and ICs, Bruges, Belgium, 2012, pp. 379-400.
Crossref
[16]
F. Udrea and D. Garner, SOI power devices, Electronic & Communication Engineering Journal, vol. 12, no. 1, pp. 27-40, 2000.
Crossref Google Scholar
[17]
M. Stoisiek, K. G. Oppermann, U. Schwalke, and D. Takacs, A dielectric isolated high-voltage IC-technology for off-line applications, in Proc. of 7th Int. Symp. Power Semiconductor Devices and IC’s: ISPSD’95, Yokohama, Japan, 1995, pp. 325-329.
[18]
K. Watabe, H. Akiyama, T. Terashima, S. Nobuto, M. Yamawaki, and T. Hirao, A 0.8 μm high voltage IC using newly designed 600 V lateral IGBT on thick buried-oxide SOI, in Proc. of 8th Int. Symp. Power Semiconductor Devices and ICs. ISPSD’96, Maui, HI, USA, 1996, pp. 151-154.
[19]
J. A. Appels and H. M. J. Vaes, High voltage thin layer devices (RESURF devices), in Proc. of 1979 Int. Electron Devices Meeting, Washington, DC, USA, 1979, pp. 238-241.
Crossref
[20]
H. M. J. Vaes and J. A. Appels, High voltage, high current lateral devices, in Proc. of 1980 Int. Electron Devices Meeting, Washington, DC, USA, 1980, pp. 87-90.
Crossref
[21]
D. R. Disney, A. K. Paul, M. Darwish, R. Basecki, and V. Rumennik, A new 800 V lateral MOSFET with dual conduction paths, in Proc. of 13th Int. Symp. Power Semiconductor Devices & ICs. IPSD’01, Osaka, Japan, 2001, pp. 399-402.
[22]
M. Qiao, Y. F. Li, X. Zhou, Z. J. Li, and B. Zhang, A 700-V junction-isolated triple RESURF LDMOS with N-type top layer, IEEE Electron Dev. Lett., vol. 35, no. 7, pp. 774-776, 2014.
Crossref Google Scholar
[23]
M. Qiao, C. Z. Li, Y. H. Liu, Y. R. Wang, Z. J. Li, and B. Zhang, Design of a novel triple reduced surface field LDMOS with partial linear variable doping N-type top layer, Superlattice. Microst., vol. 93, pp. 242-247, 2016.
Crossref Google Scholar
[24]
M. Imam, Z. Hossain, M. Quddus, J. Adams, C. Hoggatt, T. Ishiguro, and R. Nair, Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process, IEEE Trans. Electron Dev., vol. 50, no. 7, pp. 1697-1700, 2003.
Crossref Google Scholar
[25]
M. M. H. Iqbal, F. Udrea, and E. Napoli, On the static performance of the RESURF LDMOSFETS for power ICs, in Proc. of 21th Int. Symp. Power Semiconductor Devices & IC’s, Barcelona, Spain, 2009, pp. 247-250.
Crossref
[26]
M. Qiao, Y. R. Wang, X. Zhou, F. Jin, H. H. Wang, Z. Wang, Z. J. Li, and B. Zhang, Analytical modeling for a novel triple RESURF LDMOS with N-top layer, IEEE Trans. Electron Dev., vol. 62, no. 9, pp. 2933-2939, 2015.
Crossref Google Scholar
[27]
M. Qiao, Y. Li, Z. Y. Yuan, L. F. Liang, Z. J. Li, and B. Zhang, A novel ultralow RON,sp triple RESURF LDMOS with sandwich N-P-N layer, IEEE Trans. Electron Dev., vol. 67, no. 12, pp. 5605-5612, 2020.
Crossref Google Scholar
[28]
H. Yilmaz, Modeling and optimization of lateral high voltage IC devices to minimize 3-D effects, in Proc. of Symp. High Voltage and Smart Power Devices, .
Crossref
[29]
E. J. Wildi, P. V. Gray, T. P. Chow, H. R. Chang, and M. Cornell, Modeling and process implementation of implanted RESURF type devices, in Proc. of Int. Electron Devices Meeting, San Francisco, CA, USA, 1982, pp. 268-271.
Crossref
[30]
M. A. Shibib, Area-efficient layout for high voltage lateral devices, U.S. Patent US5534721A, July 9, 1996.
[31]
Z. H. Li, X. Hong, M. Ren, B. Zhang, Z. J. Li, and M. L. Qian, A controllable high-voltage C-SenseFET by inserting the second gate, IEEE Trans. Power Electron., vol. 26, no. 5, pp. 1329-1332, 2011.
Crossref Google Scholar
[32]
S. H. Lee, C. K. Jeon, J. W. Moon, and Y. C. Choi, 700V lateral DMOS with new source fingertip design, in Proc. of 20th Int. Symp. Power Semiconductor Devices and IC’s, Orlando, FL, USA, 2008, pp. 141-144.
Crossref
[33]
M. Qiao, X. Hu, H. J. Wen, M. Wang, B. Luo, X. R. Luo, Z. Wang, B. Zhang, and Z. J. Li, A novel substrate-assisted RESURF technology for small curvature radius junction, in Proc. of 23rd Int. Symp. Power Semiconductor Devices and ICs, San Diego, CA, USA, 2011, pp. 16-19.
Crossref
[34]
M. Qiao, W. J. Wu, B. Zhang, and Z. J. Li, A novel substrate termination technology for lateral double-diffused MOSFET based on curved junction extension, Semicond. Sci. Technol., vol. 29, no. 4, p. 045002, 2014.
Crossref Google Scholar
[35]
M. Qiao, L. L. Yu, G. Dai, K. Ye, Y. R. Wang, Z. J. Li, and B. Zhang, Design of a 700 V DB-nLDMOS based on substrate termination technology, IEEE Trans. Electron Dev., vol. 62, no. 12, pp. 4121-4127, 2015.
Crossref Google Scholar
[36]
M. Qiao, L. L. Yu, H. H. Wang, F. Jin, Z. J. Li, and B. Zhang, On the progressive performance of a 700-V triple RESURF LDMOS based on substrate termination technology, in Proc. of 13th IEEE Int. Conf. Solid-State and Integrated Circuit Technology, Hangzhou, China, 2016, pp. 385-388.
Crossref
[37]
M. Qiao, Z. K. Wang, Y. R. Wang, L. L. Yu, Q. Q. Xiao, Z. J. Li, and B. Zhang, 3-D edge termination design and Ron,sp-BV model of a 700-V triple RESURF LDMOS with N-type top layer, IEEE Trans. Electron Dev., vol. 64, no. 6, pp. 2579-2586, 2017.
Crossref Google Scholar
[38]
W. T. Zhang, J. Zu, X. H. Zhu, S. Zhang, Z. L. Zhang, N. L. He, B. Y. He, M. Qiao, Z. J. Li, and B. Zhang, Mechanism and experiments of a novel dielectric termination technology based on equal-potential principle, in Proc. of 32nd Int. Symp. Power Semiconductor Devices and ICs, Vienna, Austria, 2020, pp. 38-41.
Crossref
[39]
Y. Sugawara and T. Kamei, Field reduction regions for compact high-voltage IC’s, IEEE Trans. Electron Dev., vol. 34, no. 8, pp. 1816-1822, 1987.
Crossref Google Scholar
[40]
E. Flack, W. Gerlach, and J. Korec, Influence of interconnections onto the breakdown voltage of planar high-voltage P-N junctions, IEEE Trans. Electron Dev., vol. 40, no. 2, pp. 439-447, 1993.
Crossref Google Scholar
[41]
J. Perez-Gonzalez, J. Sonsky, A. Heringa, J. Benson, P. Y. Chiang, C. W. Yao, and R. Y. Sua, HCI reliability control in HV-PMOS transistors: Conventional EDMOS vs. dielectric RESURF and lateral field plates, in Proc. of 21st Int. Symp. Power Semiconductor Devices & IC’s, Barcelona, Spain, 2009, pp. 61-64.
Crossref
[42]
N. Sakurai, M. Nemoto, H. Arakawa, and Y. Sugawara, A three-phase inverter IC for AC220 V with a drastically small chip size and highly intelligent functions, in Proc. of 5th Int. Symp. Power Semiconductor Devices and ICs, Monterey, CA, USA, 1993, pp. 310-315.
[43]
L. H. Chang, , and , Bonding pad with circular exposed area and method thereof, U.S. Patent US5366589, November 22, 1994.
[44]
T. Fujihira, Y. Yano, S. Obinata, N. Kumagai, and K. Sakurai, Self-shielding: New high-voltage inter-connection technique for HVICs, in Proc. of 8th Int. Symp. Power Semiconductor Devices and ICs, Maui, HI, USA, 1996, pp. 231-234.
[45]
S. L. Kim, C. K. Jeon, M. H. Kim, and J. J. Kim, Realization of robust 600V high side gate drive IC with a new isolated self-shielding structure, in Proc. of 17th Int. Symp. Power Semiconductor Devices and ICs, Santa Barbara, CA, USA, 2005, pp. 143-146.
[46]
T. Terashima, K. Shimizu, and S. Hine, A new level-shifting technique by divided RESURF structure, in Proc. of 9th Int. Symp. Power Semiconductor Devices and IC’s, Weimar, Germany, 1997, pp. 57-60.
[47]
K. Shimizu and T. Terashima, The 2nd Generation divided RESURF structure for high voltage ICs, in Proc. of 20th Int. Symp. Power Semiconductor Devices and IC’s, Orlando, FL, USA, 2008, pp. 311-314.
Crossref
[48]
E. Falck, W. Gerlach, and J. Korec, On the blocking capability of a planar P-N junction under the influence of a high-voltage interconnection-a 3-D simulation, IEEE Trans. Electron Dev., vol. 43, no. 1, pp. 165-169, 1996.
Crossref Google Scholar
[49]
R. A. Martin, S. A. Buhler, and G. Lao, 850V NMOS driver with active outputs, in Proc. of Int. Electron Devices Meeting, San Francisco, CA, USA, 1984, pp. 266-269.
Crossref
[50]
B. Zhang, Z. J. Li, S. D. Hu, and X. R. Luo, Field enhancement for dielectric layer of high-voltage devices on silicon on insulator, IEEE Trans. Electron Dev., vol. 56, no. 10, pp. 2327-2334, 2009.
Crossref Google Scholar
[51]
Z. J. Li, B. Zhang, X. R. Luo, S. D. Hu, J. Fang, Z. H. Li, M. Qiao, and Y. F. Guo, The rule of field enhancement for buried dielectric layer of SOI high voltage devices, in Proc. of Int. Conf. Communications, Circuits and Systems, Kokura, Japan, 2007, pp. 1302-1305.
Crossref
[52]
A. S. Grove, Physics and Technology of Semiconductor Devices. New York, NY, USA: John Wiley and Sons, Inc., 1967.
[53]
T. Letavic, J. Petruzzello, J. Claes, P. Eggenkamp, E. Janssen, and A. van der Wal, 650V SOI LIGBT for switch-mode power supply application, in Proc. of 18th Int. Symp. Power Semiconductor Devices and IC’s, Naples, Italy, 2006, pp. 1-4.
[54]
S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, and R. Pinker, High-breakdown-voltage devices in ultra-thin SOI, in Proc. of 1991 IEEE Int. SOI Conf., Vail Valley, CO, USA, 1991, pp. 150&151.
[55]
W. T. Zhang, Z. Y. Zhan, Y. Yu, S. K. Cheng, Y. Gu, S. Zhang, X. R. Luo, Z. H. Li, M. Qiao, Z. J. Li, and B. Zhang, Novel superjunction LDMOS (>950 V) with a thin layer SOI, IEEE Electron Dev. Lett., vol. 38, no. 11, pp. 1555-1558, 2017.
Crossref Google Scholar
[56]
S. D. Zhang, J. K. O. Sin, T. M. L. Lai, and P. K. Ko, Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices, IEEE Trans. Electron Dev., vol. 46, no. 5, pp. 1036-1041, 1999.
Crossref Google Scholar
[57]
X. R. Luo, B. Zhang, and Z. J. Li, A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer, Solid-State Electron., vol. 51, no. 3, pp. 493-499, 2007.
Crossref Google Scholar
[58]
H. Funaki, Y. Yamaguchi, K. Hirayama, and A. Nakagawa, New 1200 V MOSFET structure on SOI with SIPOS shielding layer, in Proc. of 10th Int. Symp. Power Semiconductor Devices and ICs, Kyoto, Japan, 1998, pp. 25-28.
[59]
N. Yasuhara, A. Nakagawa, and K. Furukawa, SOI device structures implementing 650 V high voltage output devices on VLSIs, in Proc. of Int. Electron Devices Meeting, Washington, DC, USA, 1991, pp. 141-144.
[60]
X. R. Luo, B. Zhang, Z. J. Li, Y. F. Guo, X. W. Tang, and Y. Liu, A novel 700-V SOI LDMOS with double-sided trench, IEEE Electron Dev. Lett., vol. 28, no. 5, pp. 422-424, 2007.
Crossref Google Scholar
[61]
X. R. Luo, Z. J. Li, B. Zhang, Y. F. Guo, and X. W. Tang, A novel structure and its breakdown mechanism of an SOI high voltage device with a shielding trench, (in Chinese), Chin.J. Semicond., vol. 26, no. 11, pp. 2154-2158, 2005.
Google Scholar
[62]
W. Fulop, Calculation of avalanche breakdown voltages of silicon P-N junctions, Solid-State Electron., vol. 10, no. 1, pp. 39-43, 1967.
Crossref Google Scholar
[63]
S. M. Sze and K. K. Ng, Physics of Semiconductor Devices. New York, NY, USA: John Wiley & Sons, 2006.
Crossref
[64]
W. T. Zhang, S. Pu, C. L. Lai, L. Ye, S. K. Cheng, S. Zhang, B. Y. He, Z. Wang, X. R. Luo, M. Qiao, et al., Non-full depletion mode and its experimental realization of the lateral superjunction, in Proc. of 30th Int. Symp. Power Semiconductor Devices and ICs, Chicago, IL, USA, 2018, pp. 475-478.
Crossref
[65]
S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, and R. Pinker, Realization of high breakdown voltage (>700V) in thin SOI devices, in Proc. of 3rd Int. Symp. Power Semiconductor Devices & ICs, Baltimore, MD, USA, 1991, pp. 31-35.
[66]
S. D. Zhang, J. K. O. Sin, T. M. L. Lai, and P. K. Ko, Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices, IEEE Trans. Electron Dev., vol. 46, no. 5, pp. 1036-1041, 1999.
Crossref Google Scholar
[67]
B. X. Duan, B. Zhang, and Z. J. Li, A new reduced bulk field (REBULF) high-voltage LDMOS with N+-floating layer, in Proc. of Int. Conf. Communications, Circuits and Systems, Guilin, China, 2006, pp. 2709-2712.
Crossref
[68]
J. B. Cheng, B. Zhang, and Z. J. Li, A novel 1200-V LDMOSFET with floating buried layer in substrate, IEEE Electron Dev. Lett., vol. 29, no. 6, pp. 645-647, 2008.
Crossref Google Scholar
[69]
M. Qiao, B. Zhang, Z. J. Li, and J. Fang, Analysis of back-gate effect on breakdown behaviour of over 600 V SOI LDMOS transistors, Electron. Lett., vol. 43, no. 22, pp. 1231-1233, 2007.
Crossref Google Scholar
[70]
B. Zhang, J. B. Cheng, M. Qiao, and Z. J. Li, REBULF technology for bulk silicon and SOI lateral high-voltage devices, in Proc. of 9th Int. Conf. Solid-State and Integrated-Circuit Technology, Beijing, China, 2008, pp. 164-167.
[71]
S. G. Nassif-Khalil and C. A. T. Salama, Super junction LDMOST in silicon-on-sapphire technology (SJ- LDMOST), in Proc. of 14th Int. Symp. Power Semiconductor Devices and ICs, Sante Fe, NM, USA, 2002, pp. 81-84.
[72]
B. Zhang, W. T. Zhang, Z. H. Li, M. Qiao, and Z. J. Li, Equivalent substrate model for lateral super junction device, IEEE Trans. Electron Dev., vol. 61, no. 2, pp. 525-532, 2014.
Crossref Google Scholar
[73]
B. Zhang, L. Chen, J. Wu, and Z. J. Li, SLOP-LDMOS-a novel super-junction concept LDMOS and its experimental demonstration, in Proc. of Int. Conf. Communications, Circuits and Systems, Hong Kong, China, 2005, p. 1402.
[74]
B. Zhang, W. L. Wang, W. J. Chen, Z. H. Li, and Z. J. Li, High-voltage LDMOS with charge-balanced surface low on-resistance path layer, IEEE Electron Dev. Lett., vol. 30, no. 8, pp. 849-851, 2009.
Crossref Google Scholar
[75]
M. Rub, M. Bar, G. Deml, H. Kapels, M. Schmitt, S. Sedlmaier, C. Tolksdorf, and A. Willmeroth, A 600V 8.7Ohmmm2 lateral superjunction transistor, in Proc. of 18thInt. Symp. Power Semiconductor Devices and IC’s, Naples, Italy, 2006, pp. 1-4.
[76]
S. Honarkhah, S. Nassif-Khalil, and C. A. T. Salama, Back-etched super-junction LDMOST on SOI, in Proc. of 30th European Solid-State Circuits Conf., Leuven, Belgium, 2004, pp. 117-120.
[77]
I. Y. Park and C. A. T. Salama, CMOS compatible super junction LDMOST with N-buffer layer, in Proc. of 17th Int. Symp. Power Semiconductor Devices and ICs, Santa Barbara, CA, USA, 2005, pp. 163-166.
[78]
S. G. Nassif-Khalil, L. Z. Hou, and C. A. T. Salama, SJ/RESURF LDMOST, IEEE Trans. Electron Dev., vol. 51, no. 7, pp. 1185-1191, 2004.
Crossref Google Scholar
[79]
R. Ng, F. Udrea, K. Sheng, K. Ueno, G. A. J. Amaratunga, and M. Nishiura, Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI, in Proc. of 13th Int. Symp. Power Semiconductor Devices & ICs, Osaka, Japan, 2001, pp. 395-398.
[80]
Y. F. Guo, J. F. Yao, B. Zhang, H. Lin, and C. C. Zhang, Variation of lateral width technique in SOI high-voltage lateral double-diffused metal-oxide-semiconductor transistors using high-K dielectric, IEEE Electron Dev. Lett., vol. 36, no. 3, pp. 262-264, 2015.
Crossref Google Scholar
[81]
Z. Cao, B. X. Duan, S. Yuan, H. J. Guo, J. M. Lv, T. T. Shi, and Y. T. Yang, Novel superjunction LDMOS with multi-floating buried layers, in Proc. of 29th Int. Symp. Power Semiconductor Devices and IC’s, Sapporo, Japan, 2017, pp. 283-286.
Crossref
[82]
W. T. Zhang, R. Wang, S. K. Cheng, Y. Gu, S. Zhang, B. Y. He, M. Qiao, Z. J. Li, and B. Zhang, Optimization and experiments of lateral semi-superjunction device based on normalized current-carrying capability, IEEE Electron Dev. Lett., vol. 40, no. 12, pp. 1969-1972, 2019.
Crossref Google Scholar
[83]
J. B. Cheng, B. Zhang, and Z. J. Li, A superjunction LDMOST with a floating oppositely doped buried layer in substrate, in Proc. of 10th IEEE Int. Conf. Solid-State and Integrated Circuit Technology, Shanghai, China, 2010, pp. 917-919.
Crossref
[84]
B. X. Duan, Y. T. Yang, and B. Zhang, New superjunction LDMOS with N-type charges’ compensation layer, IEEE Electron Dev. Lett., vol. 30, no. 3, pp. 305-307, 2009.
Crossref Google Scholar
[85]
S. K. Panigrahi, U. Gogineni, M. S. Baghini, and F. Iravani, 120 V super junction LDMOS transistor, in Proc. of Int. Conf. Electron Devices and Solid-state Circuits, Hong Kong, China, 2013, pp. 1&2.
Crossref
[86]
G. P. V. Pathirana, F. Udrea, R. Ng, D. M. Garner, and G. A. J. Amaratunga, 3D-RESURF SOI LDMOSFET for RF power amplifiers, in Proc. of 15th Int. Symp. Power Semiconductor Devices and ICs, Cambridge, UK, 2003, pp. 278-281.
[87]
M. J. Lin, T. H. Lee, F. L. Chang, C. W. Liaw, and H. C. Cheng, Lateral superjunction reduced surface field structure for the optimization of breakdown and conduction characteristics in a high-voltage lateral double diffused metal oxide field effect transistor, Japanese J. Appl. Phys., vol. 42, no. 12, p. 7227, 2003.
Crossref Google Scholar
[88]
B. Zhang, W. T. Zhang, J. Zu, M. Qiao, S. Zhang, Z. L. Zhang, B. Y. He, and Z. J. Li, Novel homogenization field technology in lateral power devices, IEEE Electron Dev. Lett., vol. 41, no. 11, pp. 1677-1680, 2020.
Crossref Google Scholar
[89]
G. S. Zhang, W. T. Zhang, J. Q. He, X. H. Zhu, S. Zhang, J. C. Zhao, Z. Zhang, M. Qiao, X. Zhou, Z. J. Li, et al., Experiments of a novel low on-resistance LDMOS with 3-D floating vertical field plate, in Proc. of 17th Int. Symp. Power Semiconductor Devices and ICs, Shanghai, China, 2019, pp. 507-510.
Crossref
[90]
Z. G. Yu, X. B. Su, Z. H. Chen, J. X. Zou, J. H. Wei, H. Zhang, and Y. Xue, A 12-bit 250-MS/s charge-domain pipelined analog-to-digital converter with feed-forward common-mode charge control, Tsinghua Science and Technology, vol. 23, no. 1, pp. 87-94, 2018.
Crossref Google Scholar
[91]
X. Wang, S. Fan, H. Zhao, L. Lin, Q. Fang, H. Tang, and A. Wang, Whole-Chip ESD protection design for RF and AMS ICs, Tsinghua Science and Technology, vol. 15, no. 3, pp. 265-274, 2010.
Crossref Google Scholar
[92]
J. Zhang, H. Wu, W. J. Chen, S. J. Wei, and H. Chen, Design and tool flow of a reconfigurable asynchronous neural network accelerator, Tsinghua Science and Technology, vol. 26, no. 5, pp. 565-573, 2021.
Crossref Google Scholar
[93]
K. Y. R. Wong, M. H. Kwan, F. W. Yao, M. W. Tsai, Y. S. Lin, Y. C. Chang, P. C. Chen, R. Y. Su, J. J. Yu, F. J. Yang, et al., A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems, in Proc. of Int. Electron Devices Meeting, Washington, DC, USA, 2015, pp. 9.5.1-9.5.4.
[94]
K. J. Chen, O. Häberlen, A. Lidow, C. L. Tsai, T. Ueda, Y. Uemoto, and Y. F. Wu, GaN-on-Si power technology: Devices and applications, IEEE Trans. Electron Dev., vol. 64, no. 3, pp. 779-795, 2017.
Crossref Google Scholar
[95]
Navitas Semiconductor, 650 V GaNFastTM power IC, NV6113datasheet, https://www.alldatasheetcn.com/datasheet-pdf/pdf/1170434/ETC1/NV6113.html, 2018.
[96]
M. Alexandru, V. Banu, X. Jordà, J. Montserrat, M. Vellvehi, D. Tournier, J. Millán, and P. Godignon, SiC integrated circuit control electronics for high-temperature operation, IEEE Trans. Indust. Electron., vol. 62, no. 5, pp. 3182-3191, 2015.
Crossref Google Scholar
[97]
A. Abbasi, S. Roy, R. Murphree, A. U. Rashid, M. M. Hossain, P. Y. Lai, J. Fraley, T. Erlbacher, Z. Chen, and A. Mantooth, Characterization of a silicon carbide BCD process for 300 oC circuits, in Proc. of IEEE 7th Workshop on Wide Bandgap Power Devices and Applications, Raleigh, NC, USA, 2019, pp. 231-236.
Crossref
[98]
S. Tanaka, Heterogenous integration technology using wafer-to-wafer transfer, in Proc. of 2015 IEEE Int. Ultrasonics Symp. (IUS), Taipei, China, 2015, pp. 1-5.
Crossref
[99]
J. H. Lau, Heterogeneous Integrations. Singapore: Springer, 2019.
Crossref
Tsinghua Science and Technology
Volume 27 Issue 3,
June 2022
Pages 495-511
DOI: 10.26599/TST.2021.9010035
Cite this article:
Zhang B, Zhang W, Zhu L, et al. Review of Technologies for High-Voltage Integrated Circuits. Tsinghua Science and Technology, 2022, 27(3): 495-511. https://doi.org/10.26599/TST.2021.9010035

3860

Views

808

Downloads

9

Crossref

6

Web of Science

9

Scopus

0

CSCD

Altmetrics
Received: 28 February 2021
Accepted: 08 April 2021
Published: 13 November 2021
© The author(s) 2022

The articles published in this open access journal are distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/).
Return