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Open Access

Near-Threshold Wide-Voltage Design Review

National Application Specific Integrated Circuit (ASIC) Center, Southeast University, Nanjing 210096, China
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Abstract

This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower, and the energy efficiency is increased by 3–4 times.

Keywords

Near Threshold Voltage (NTV)wide-voltage memoryresilient logic designlow voltage Radio Frequency (RF)timing analysis

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Tsinghua Science and Technology
Volume 28 Issue 4,
August 2023
Pages 696-718
DOI: 10.26599/TST.2022.9010064
Cite this article:
Zhao Y, Yang J, Chen C, et al. Near-Threshold Wide-Voltage Design Review. Tsinghua Science and Technology, 2023, 28(4): 696-718. https://doi.org/10.26599/TST.2022.9010064

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Received: 06 September 2021
Revised: 22 November 2021
Accepted: 07 December 2022
Published: 06 January 2023
© The author(s) 2023.

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