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Open Access

Near-Threshold Wide-Voltage Design Review

National Application Specific Integrated Circuit (ASIC) Center, Southeast University, Nanjing 210096, China
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Abstract

This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower, and the energy efficiency is increased by 3–4 times.

References

[1]
S. K. Hsu, A. Agarwal, M. A. Anders, S. K. Mathew, H. Kaul, F. Sheikh, and R. K. Krishnamurthy, A 280 mV-to-1.1 V 256b reconfigurable SIMD vector permutation engine with 2-Dimensional shuffle in 22 nm Tri-gate CMOS, IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 118127, 2013.
[2]
F. Moradi, D. T. Wisland, H. Mahmoodi, A. Peiravi, S. Aunet, and T. V. Cao, New subthreshold concepts in 65 nm CMOS technology, in Proc. 10th Int. Symp. on Quality Electronic Design, San Jose, CA, USA, 2009, pp. 162166.
[3]
B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, et al., Energy-efficient subthreshold processor design, IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 8, pp. 11271137, 2009.
[4]
S. Chatterjee, Y. Tsividis, and P. Kinget, 0.5-V analog circuit techniques and their application in OTA and filter design, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 23732387, 2005.
[5]
A. Balankutty, S. A. Yu, Y. Feng, and P. R. Kinget, A 0.6-V zero-IF/low-IF receiver with integrated fractional-N synthesizer for 2.4-GHz ISM-band applications, IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 538553, 2010.
[6]
P. Yang, X. Ye, Y. Zhao, W. Zhang, S. Huang, Y. Huang, and Y. Wang, An error detecting scheme with input offset regulation for enhancing reliability of ultralow-voltage SRAM, Microelectron. Reliab., vol. 114, p. 113788, 2020.
[7]
J. Yang, H. Ji, Y. Guo, J. Zhu, Y. Zhuang, Z. Li, X. Liu, and L. Shi, A double sensing scheme with selective bitline voltage regulation for ultralow-voltage timing speculative SRAM, IEEE J. Solid-State Circuits, vol. 53, no. 8, pp. 24152426, 2018.
[8]
H. Attarzadeh and M. Sharifkhani, An auto-calibrated, dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier, Microelectron. J., vol. 45, no. 6, pp. 781792, 2014.
[9]
N. Verma and A. P. Chandrakasan, A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141149, 2008.
[10]
E. Karl, D. Sylvester, and D. Blaauw, Timing error correction techniques for voltage-scalable on-chip memories, in Proc. IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, 2005, pp. 35633566.
[11]
M. Khayatzadeh, M. Saligane, J. Wang, M. Alioto, D. Sylvester, and D. Sylvester, 17.3 a reconfigurable dual-port memory with error detection and correction in 28 nm FDSOI, in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2016, pp. 310312.
[12]
I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650658, 2009.
[13]
S. Shen, T. Shao, X. Shang, Y. Guo, M. Ling, J. Yang, and L. Shi, TS cache: A fast cache with timing-speculation mechanism under low supply voltages, IEEE Trans. Very Large Scale Integr. Syst., vol. 28, no. 1, pp. 252262, 2020.
[14]
Y. Zhou, H. Cai, L. Xie, M. Han, M. Liu, S. Xu, B. Liu, W. Zhao, and J. Yang, A self-timed voltage-mode sensing scheme with successive sensing and checking for STT-MRAM, IEEE Trans. Circuits Syst. I: Regular Papers, vol. 67, no. 5, pp. 16021614, 2020.
[15]
Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto, Comparing voltage adaptation performance between replica and in-situ timing monitors, in Proc. 2018 IEEE/ACM Int. Conf. on Computer-Aided Design, San Diego, CA, USA, 2018, pp. 18.
[16]
S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, A self-tuning DVS processor using delay-error detection and correction, IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792804, 2006.
[17]
S. Das, C. Tokunaga, S. Pant, W. H. Ma, S. Kalaiselvan, K. Lai, D. M. Bull, and D. T. Blaauw, Razorii: In situ error detection and correction for PVT and SER tolerance, IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 3248, 2009.
[18]
M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D. M. Harris, D. Blaauw, and D. Sylvester, Bubble razor: Eliminating timing margins in an ARM cortex-M3 processor in 45 nm CMOS using architecturally independent error detection and correction, IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 6681, 2013.
[19]
I. Kwon, S. Kim, D. Fick, M. Kim, Y. P. Chen, and D. Sylvester, Razor-lite: A light-weight register for error detection by observing virtual supply rails, IEEE J. Solid-State Circuits, vol. 49, no. 9, pp. 20542066, 2014.
[20]
Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, N. Pinckney, M. Alioto, D. Blaauw, and D. Sylvester, iRazor: Current-based error detection and correction scheme for PVT variation in 40-nm ARM Cortex-R4 processor, IEEE J. Solid-State Circuits, vol. 53, no. 2, pp. 619631, 2018.
[21]
P. N. Whatmough, S. Das, and D. M. Bull, A low-power 1-GHz Razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65-nm CMOS, IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 8494, 2014.
[22]
S. Kim and M. Seok, Variation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique, IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 14781490, 2015.
[23]
X. Shang, W. Shan, J. Xu, M. Lu, Y. Xiang, L. Shi, and J. Yang, A 0.46 V–1.1 V transition-detector with in-situ timing-error detection and correction based on pulsed-latch design in AES accelerator, in Proc. 2018 IEEE Asian Solid-State Circuits Conf. (A-SSCC), Tainan, China, 2018, pp. 14.
[24]
W. Shan, X. Shang, L. Shi, W. Dai, and J. Yang, Timing error prediction AVFS with detection window tuning for wide-operating-range ICs, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 65, no. 7, pp. 933937, 2018.
[25]
H. Reyserhove and W. Dehaene, Margin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOS, IEEE J. Solid-State Circuits, vol. 53, no. 7, pp. 21012113, 2018.
[26]
W. Jin, S. Kim, W. He, Z. Mao, and M. Seok, In situ error detection techniques in ultralow voltage pipelines: Analysis and optimizations, IEEE Trans. Very Large Scale Integr. Syst., vol. 25, no. 3, pp. 10321043, 2017.
[27]
C. Lin, W. He, Y. Sun, B. Pei, Z. Mao, and M. Seok, 25.8 a near-threshold-voltage network-on-chip with a metastability error detection and correction technique for supporting a quad-voltage/frequency-domain ultra-low-power system-on-a-chip, in Proc. 2020 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2020, pp. 394396.
[28]
J. Zhou, L. Xin, Y. H. Lam, C. Wang, K. H. Chang, J. Lan, and M. Je, HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs, in Proc. 2013 IEEE Asian Solid-State Circuits Conf., Singapore, 2013, pp. 129132.
[29]
M. A. Ealey and J. F. Mark, Continuous facesheet low voltage deformable mirrors, Opt. Eng., vol. 29, no. 10, pp. 11911198, 1990.
[30]
S. Akui, K. Seno, M. Nakai, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, Dynamic voltage and frequency management for a low-power embedded microprocessor, in Proc. 2004 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2005, pp. 2835.
[31]
K. Agarwal and K. J. Nowka, Dynamic power management by combination of dual static supply voltages, in Proc. 8th Int. Symp. on Quality Electronic Design, San Jose, CA, USA, 2007, pp. 8592.
[32]
K. A. Bowman, J. W. Tschanz, S. L. L. Lu, P. A. Aseron, M. M. Khellah, A. Raychowdhury, B. M. Geuskens, C. Tokunaga, C. B. Wilkerson, T. Karnik, et al., A 45 nm resilient microprocessor core for dynamic variation tolerance, IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 194208, 2011.
[33]
I. Ikenaga, M. Nomura, S. Suenaga, H. Sonohara, Y. Horikoshi, T. Saito, Y. Ohdaira, Y. Nishio, T. Iwashita, M. Satou, et al., A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines, IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 832840, 2012.
[34]
R. Salvador, A. Sanchez, X. Fan, and T. Gemmeke, A Cortex-M3 based MCU featuring AVS with 34nW static power, 15.3pJ/inst. active energy, and 16% power variation across process and temperature, in Proc. ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conf. (ESSCIRC), Dresden, Germany, 2018, pp. 278281.
[35]
J. Kim, K. Choi, Y. Kim, W. Kim, K. Do, and J. Choi, Delay monitoring system with multiple generic monitors for wide voltage range operation, IEEE Trans. Very Large Scale Integr. Syst., vol. 26, no. 1, pp. 3749, 2018.
[36]
M. Saligane, J. Lee, Q. Dong, M. Yasuda, K. Kumeno, F. Ohno, S. Miyoshi, M. Kawaminami, D. Blaauw, and D. Sylvester, An adaptive body-Biaslna SoC using in situ slack monitoring for runtime replica calibration, in Proc. 2018 IEEE Symp. on VLSI Circuits, Honolulu, HI, USA, 2018, pp. 6364.
[37]
W. Shan, X. Shang, X. Wan, H. Cai, C. Zhang, and J. Yang, A wide-voltage-range half-path timing error-detection system with a 9-transistor transition-detector in 40-nm CMOS, IEEE Trans. Circuits Syst. I: Regular Papers, vol. 66, no. 6, pp. 22882297, 2019.
[38]
W. Shan, W. Dai, C. Zhang, H. Cai, P. Liu, J. Yang, and L. Shi, TG-SPP: A one-transmission-gate short-path padding for wide-voltage-range resilient circuits in 28-nm CMOS, IEEE J. Solid-State Circuits, vol. 55, no. 5, pp. 14221436, 2020.
[39]
W. Shan, W. Dai, L. Wan, M. Lu, L. Shi, M. Seok, and J. Yang, A bi-directional, zero-latency adaptive clocking circuit in a 28-nm wide AVFS system, IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 826836, 2020.
[40]
W. Shan, L. Wan, X. Liu, X. Shang, W. Dai, S. Shao, J. Yang, and L. Shi, A low overhead, within-a-cycle adaptive clock stretching circuit with wide operating range in 40-nm CMOS, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 65, no. 11, pp. 17181722, 2018.
[41]
L. Liu and Z. Wang, Analysis and design of a low-voltage RF CMOS mixer, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 53, no. 3, pp. 212216, 2006.
[42]
H. Lakdawala, M. Schaecher, C. T. Fu, R. Limaye, J. Duster, Y. Tan, A Balankutty, E. Alpman, C. Lee, S. Suzuki, et al., 32nm x86 OS-compliant PC on-chip with dual-core atom® processor and RF WiFi transceiver, in Proc. 2012 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2012, pp. 6264.
[43]
J. Zhang, D. Zhao, and X. You, A 20-GHz 1.9-mW LNA using gm-boost and current-reuse techniques in 65-nm CMOS for satellite communications, IEEE J. Solid-State Circuits, vol. 55, no. 10, pp. 27142723, 2020.
[44]
M. Parvizi, K. Allidina, and M. N. El-Gamal, Short channel output conductance enhancement through forward body biasing to realize a 0.5 V 250 μW 0.6-4.2 GHz current-reuse CMOS LNA, IEEE J. Solid-State Circuits, vol. 51, no. 3, pp. 574586, 2016.
[45]
C. H. Chang, A forward-body-bias CMOS LNA with ultra-low device junction leakage using intrinsic self-balanced pseudo resistor, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 66, no. 4, pp. 697701, 2019.
[46]
D. Markovic, C. C. Wang, L. P. Alarcon, T. T. Liu, and J. M. Rabaey, Ultralow-power design in near-threshold region, Proc. IEEE, vol. 98, no. 2, pp. 237252, 2010.
[47]
M. Tamura, H. Takano, S. Shinke, H. Fujita, H. Nakahara, N. Suzuki, Y. Nakada, Y. Shinohe, S. Etou, T. Fujiwara, and Y. Katayama, A 0.5 V BLE transceiver with a 1.9 mW RX achieving –96.4 dBm sensitivity and 4.1 dB adjacent channel rejection at 1 MHz Offset in 22 nm FDSOI, in Proc. of IEEE ISSCC Dig. Tech., San Francisco, CA, USA, 2020, pp. 468470.
[48]
T. S. Chao, Y. L. Lo, W. B. Yang, and K. H. Cheng, Designing ultra-low voltage PLL using a bulk-driven technique, in 2009 Proc. ESSCIRC, Athens, Greece, 2009, pp. 388391.
[49]
S. G. Kim, J. Rhim, D. H. Kwon, M. H. Kim, and W. Y. Choi, A low-voltage PLL with a supply-noise compensated feedforward ring VCO, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 63, no. 6, pp. 548552, 2016.
[50]
B. Ghafari, L. Koushaeian, and F. Goodarzy, New architecture for an ultra low power and low noise PLL for biomedical applications, in Proc. 2013 IEEE Global High Tech Congress on Electronics, Shenzhen, China, 2013, pp. 6162.
[51]
J. W. Moon, S. G. Kim, D. H. Kwon, and W. Y. Choi, A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation, in Proc. 2014 Custom Integrated Circuits Conf., San Jose, CA, USA, 2014, pp. 14.
[52]
H. H. Hsieh, C. T. Lu, and L. H. Lu, A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-μm CMOS, in Proc. 2007 IEEE Symp. On VLSI Circuits, Kyoto, Japan, 2007, pp. 164165.
[53]
H. Liu, D. Tang, Z. Sun, W. Deng, H. C. Ngo, K. Okada, and A. Matsuzawa, A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of –246 dB for IoT applications in 65nm CMOS, in Proc. 2018 IEEE Int. Solid - State Circuits Conf., 2018, San Francisco, CA, USA, pp. 246248.
[54]
M. Tamura, H. Takano, S. Shinke, H. Fujita, H. Nakahara, N. Suzuki, Y. Nakada, Y. Shinohe, S. Etou, T. Fujiwara, et al., 30.5 A 0.5 V BLE transceiver with a 1.9 mW RX achieving –96.4 dBm sensitivity and 4.1 dB adjacent channel rejection at 1 MHz offset in 22 nm FDSOI, in Proc. 2020 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2020, pp. 468470.
[55]
C. Chen and J. Wu, 0.6-V 2.1-mW RF receiver based on passive mixing and master–slave common-mode rejection technique in 65ṅm CMOS, Electron. Lett., vol. 52, no. 5, pp. 335336, 2016.
[56]
M. Seok, S. Hanson, Y. S. Lin, Z. Foo, D. Kim, Y. Lee, N. Liu, D. Sylvester, and D. Blaauw, The phoenix processor: A 30 pW platform for sensor applications, in Proc. 2008 IEEE Symp. on Vlsi Circuits, Honolulu, HI, USA, 2008, pp. 188189.
[57]
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, Parameter variations and impact on circuits and microarchitecture, in Proc. 2003 Design Automation Conf., Anaheim, CA, USA, 2003, pp. 338342.
[58]
F. Frustaci, P. Corsonello, and S. Perri, Analytical delay model considering variability effects in subthreshold domain, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 59, no. 3, pp. 168172, 2012.
[59]
W. L. Loh, On Latin hypercube sampling, Ann. Statist., vol. 24, no. 5, pp. 20582080, 1996.
[60]
S. Reh, P. Lethbridge, and D. Ostergaard, Quality based design and design for reliability of micro electro mechanical systems (MEMS) using probabilistic methods, in Proc. 2000 In. Conf. on Modeling and Simulation of Microsystems, San Diego, CA, USA, 2000, pp. 708711.
[61]
H. Awano and T. Sato, Efficient transistor-level timing yield estimation via line sampling, in Proc. 53rd ACM/EDAC/IEEE Design Automation Conf., Austin, TX, USA, 2016, pp. 16.
[62]
R. Kanj, R. Joshi, and S. Nassif, Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events, in Proc. 2006 43rd ACM/IEEE Design Automation Conf., San Francisco, CA, USA, 2006, pp. 6972.
[63]
R. E. Caflisch, Monte Carlo and Quasi-Monte Carlo methods, Acta Numer., vol. 7, pp. 149, 1998.
[64]
J. Chen, S. Cotofana, S. Grandhi, C. Spagnol, and E. Popovici, Inverse Gaussian distribution based timing analysis of sub-threshold CMOS circuits, Microelectron. Reliab., vol. 55, no. 12, pp. 27542761, 2015.
[65]
L. Zhang, J. Shao, and C. C. P. Chen, Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis, in Proc. 2006 Int. Symp. on Physical Design, San Jose, CA, USA, 2006, pp. 3338.
[66]
S. Ramprasath, M. Vijaykumar, and V. Vasudevan, A skew-normal canonical model for statistical static timing analysis, IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 6, pp. 23592368, 2016.
[67]
H. A. Balef, M. Kamal, A. Afzali-Kusha, and M. Pedram, All-region statistical model for delay variation based on log-skew-normal distribution, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 35, no. 9, pp. 15031508, 2016.
[68]
K. J. Chang, Accurate on-chip variation modeling to achieve design for manufacturability, in Proc. 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, 2004, pp. 219222.
[69]
J. Hong, K. Huang, P. Pong, J. D. Pan, J. Kang, and K. C. Wu, An LLC-OCV methodology for statistic timing analysis, in Proc. 2007 Int. Symp. on Vlsi Design, Automation and Test, Hsinchu, China, 2007, pp. 14.
[70]
A. Mutlu, J. Le, R. Molina, and M. Celik, A parametric approach for handling local variation effects in timing analysis, in Proc. 2009 46th ACM/IEEE Design Automation Conf., Francisco, CA, USA, 2009, pp. 126129.
[71]
S. Keller, D. M. Harris, and A. J. Martin, A compact transregional model for digital CMOS circuits operating near threshold, IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 10, pp. 20412053, 2014.
[72]
M. Alioto, G. Scotti, and A. Trifiletti, A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4 metric, IEEE Trans. Circuits Syst. I: Regular Papers, vol. 64, no. 8, pp. 20732085, 2017.
[73]
J. Shiomi, T. Ishihara, and H. Onodera, Microarchitectural-level statistical timing models for near-threshold circuit design, in Proc. 20th Asia and South Pacific Design Automation Conf., Chiba, Japan, 2015, pp. 8793.
[74]
Y. Zhang and B. H. Calhoun, Fast, accurate variation-aware path timing computation for sub-threshold circuits, in Proc. 15th Int. Symp. on Quality Electronic Design, Santa Clara, CA, USA, 2014, pp. 243248.
[75]
J. Guo, P. Cao, M. Li, Y. Gong, Z. Liu, G. Bai, and J. Yang, Semi-analytical path delay variation model with adjacent gates decorrelation for subthreshold circuits, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 40, no. 5, pp. 931944, 2020.
[76]
A. B. Kahng, M. Luo, and S. Nath, SI for free: Machine learning of interconnect coupling delay and transition effects, in Proc. 2015 ACM/IEEE Int. Workshop on System Level Interconnect Prediction (SLIP), San Francisco, CA, USA, 2015, pp. 18.
[77]
A. Kahng, U. Mallappa, and L. Saul, Using machine learning to predict path-based slack from graph-based timing analysis, in Proc. 2018 IEEE 36th Int. Conf. on Computer Design (ICCD), Orlando, FL, USA, 2018, pp. 603612.
[78]
E. C. Barboza, N. Shukla, Y. Chen, and J. Hu, Machine learning-based pre-routing timing prediction with reduced pessimism, in Proc. 2019 56th ACM/IEEE Design Automation Conf. (DAC), Las Vegas, NV, USA, 2019, pp. 16.
[79]
A. B. Kahng, S. Kang, H. Lee, S. Nath, and J. Wadhwani, Learning-based approximation of interconnect delay and slew in signoff timing tools, in Proc. 2013 ACM/IEEE Int. Workshop on System Level Interconnect Prediction, Austin, TX, USA, 2013, pp. 18.
[80]
A. B. Kahng, U. Mallappa, L. Saul, and S. Tong, “Unobserved corner” prediction: Reducing timing analysis effort for faster design convergence in advanced-node design, in Proc. 2019 Design, Automation & Test in Europe Conf. & Exhibition (DATE), Florence, Italy, 2019, pp. 168173.
[81]
S. Ganapathy, R. Canal, A. Gonzalez, and A. Rubio, Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability, in Proc. 2010 Design, Automation & Test in Europe Conf. & Exhibition, Dresden, Germany, 2010, pp. 417422.
[82]
W. Bao, P. Cao, H. Cai, and A. G. Bu, A learning-based timing prediction framework for wide supply voltage design, in Proc. 2020 on Great Lakes Symp. on VLSI, New York, NY, USA, 2020, pp. 309314.
[83]
P. Cao, W. Bao, K. Wang, and T. Yang, A timing prediction framework for wide voltage design with data augmentation strategy, in Proc. 2021 26th Asia and South Pacific Design Automation Conf., Tokyo, Japan, 2021, pp. 291296.
[84]
X. Li, Y. Xu, L. Ren, W. Ge, J. Cai, X. Liu, and J. Yang, 29.8 115nA@3V ULPMark-CP score 1205 SCVR-less dynamic voltage-stacking scheme for IoT MCU, in Proc. 2021 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, 2021, pp. 100102.
Tsinghua Science and Technology
Pages 696-718
Cite this article:
Zhao Y, Yang J, Chen C, et al. Near-Threshold Wide-Voltage Design Review. Tsinghua Science and Technology, 2023, 28(4): 696-718. https://doi.org/10.26599/TST.2022.9010064

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Received: 06 September 2021
Revised: 22 November 2021
Accepted: 07 December 2022
Published: 06 January 2023
© The author(s) 2023.

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