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Regular Paper

A Non-Stop Double Buffering Mechanism for Dataflow Architecture

State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China
School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China
State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi, 214125, China
Department of Computer Science, The University of Chicago, Chicago, IL, 60637, U.S.A.
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Abstract

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataflow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

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Journal of Computer Science and Technology
Pages 145-157
Cite this article:
Tan X, Shen X-W, Ye X-C, et al. A Non-Stop Double Buffering Mechanism for Dataflow Architecture. Journal of Computer Science and Technology, 2018, 33(1): 145-157. https://doi.org/10.1007/s11390-017-1747-6

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Received: 02 September 2016
Revised: 13 March 2017
Published: 26 January 2018
©2018 LLC & Science Press, China
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