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Regular Paper

wrBench: Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems

College of Computer Science, National University of Defense Technology, Changsha 410073, China
School of Computing, University of Leeds, Leeds, LS2 9JT, U.K.
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Abstract

Cache performance is a critical design constraint for modern many-core systems. Since the cache often works in a "black-box" manner, it is difficult for the software to reason about the cache behavior to match the running software to the underlying hardware. To better support code optimization, we need to understand and characterize the cache behavior. While cache performance characterization is heavily studied on traditional x86 architectures, there is little work for understanding the cache implementations on emerging ARMv8-based many-cores. This paper presents a comprehensive study to evaluate the cache architecture design on three representative ARMv8 multi-cores, Phytium 2000+, ThunderX2, and Kunpeng 920 (KP920). To this end, we develop wrBench, a micro-benchmark suite to measure the realized latency and bandwidth of caches at different memory hierarchies when performing core-to-core communication. Our evaluation provides inter-core latency and bandwidth in different cache levels and coherency states for the three ARMv8 many-cores. The quantitative performance data is shown in tables. We mine the characteristics of caches and coherency protocols by analyzing the data for the three processors, Phytium 2000+, ThunderX2, and KP920. Our paper also provides discussions and guidelines for optimizing memory access on ARMv8 many-cores.

Keywords

ARMv8 many-corecache architecturemicrobenchmarkcore-to-core communication

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Journal of Computer Science and Technology
Volume 38 Issue 6,
November 2023
Pages 1323-1338
DOI: 10.1007/s11390-021-1251-x
Cite this article:
Gao W-R, Fang J-B, Huang C, et al. wrBench: Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems. Journal of Computer Science and Technology, 2023, 38(6): 1323-1338. https://doi.org/10.1007/s11390-021-1251-x

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Received: 31 December 2020
Accepted: 14 November 2021
Published: 15 November 2023
© Institute of Computing Technology, Chinese Academy of Sciences 2023
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