AI Chat Paper
Note: Please note that the following content is generated by AMiner AI. SciOpen does not take any responsibility related to this content.
{{lang === 'zh_CN' ? '文章概述' : 'Summary'}}
{{lang === 'en_US' ? '中' : 'Eng'}}
Chat more with AI
Article Link
Collect
Submit Manuscript
Show Outline
Outline
Show full outline
Hide outline
Outline
Show full outline
Hide outline
Regular Paper

Path-Based Multicast Routing for Network-on-Chip of the Neuromorphic Processor

College of Computer Science and Technology, National University of Defense Technology, Changsha 410000, China
Show Author Information

Abstract

Network-on-Chip (NoC) is widely adopted in neuromorphic processors to support communication between neurons in spiking neural networks (SNNs). However, SNNs generate enormous spiking packets due to the one-to-many traffic pattern. The spiking packets may cause communication pressure on NoC. We propose a path-based multicast routing method to alleviate the pressure. Firstly, all destination nodes of each source node on NoC are divided into several clusters. Secondly, multicast paths in the clusters are created based on the Hamiltonian path algorithm. The proposed routing can reduce the length of path and balance the communication load of each router. Lastly, we design a lightweight microarchitecture of NoC, which involves a customized multicast packet and a routing function. We use six datasets to verify the proposed multicast routing. Compared with unicast routing, the running time of path-based multicast routing achieves 5.1x speedup, and the number of hops and the maximum transmission latency of path-based multicast routing are reduced by 68.9% and 77.4%, respectively. The maximum length of path is reduced by 68.3% and 67.2% compared with the dual-path (DP) and multi-path (MP) multicast routing, respectively. Therefore, the proposed multicast routing has improved performance in terms of average latency and throughput compared with the DP or MP multicast routing.

Electronic Supplementary Material

Download File(s)
JCST-2012-11232-Highlights.pdf (143.2 KB)

References

[1]

Akopyan F, Sawada J, Cassidy A et al. TrueNorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , 2015, 24(10): 1537–1557. DOI: 10.1109/tcad.2015.2474396.

[2]

Davies M, Srinivasa N, Lin T H et al. Loihi: A neuromorphic manycore processor with on-chip learning. IEEE Micro , 2018, 38(1): 82–99. DOI: 10.1109/mm.2018.112130359.

[3]

Navaridas J, Luján M, Plana L A, Temple S, Furber S B. Spinnaker: Enhanced multicast routing. Parallel Computing , 2015, 45: 49–66. DOI: 10.1016/j.parco.2015.01.002.

[4]

Gautrais J, Thorpe S. Rate coding versus temporal order coding: A theoretical approach. Biosystems , 1998, 48(1/2/3): 57–65. DOI: 10.1016/S0303-2647(98)00050-1.

[5]

Vainbrand D, Ginosar R. Scalable network-on-chip architecture for configurable neural networks. Microprocessors and Microsystems , 2011, 35(2): 152–166. DOI: 10.1016/j.micpro.2010.08.005.

[6]

Vu T H, Okuyama Y, Abdallah A B. Comprehensive analytic performance assessment and k-means based multicast routing algorithm and architecture for 3D-NoC of spiking neurons. ACM Journal on Emerging Technologies in Computing Systems , 2019, 15(4): 1–28. DOI: 10.1145/3340963.

[7]
Jerger N E, Peh L S, Lipasti M. Virtual circuit tree multicasting: A case for on-chip hardware multicast support. In Proc. the 2008 IEEE International Symposium on Computer Architecture, Jun. 2008, pp.229–240. DOI: 10.1109/ISCA.2008.12.
[8]

Lin X L, Ni L M. Multicast communication in multicomputer networks. IEEE Trans. Parallel and Distributed Systems , 1993, 4(10): 1105–1117. DOI: 10.1109/71.246072.

[9]
Ebrahimi M, Daneshtalab M, Neishaburi M H et al. An efficent dynamic multicast routing protocol for distributing traffic in NOCs. In Proc. the 2008 IEEE Design, Automation & Test in Europe Conference & Exhibition, Apr. 2009, pp.1064–1069. DOI: 10.1109/DATE.2009.5090822.
[10]

Ni L M, Mckinley P K. A survey of wormhole routing techniques in direct networks. Computer , 1993, 26(2):62–76. DOI: 10.1109/2.191995.

[11]

Maass, W. Networks of spiking neurons: The third generation of neural network models. Neural networks, 1997(10):1659–1671. DOI: 10.1016/S0893-6080(97)00011-7.

[12]

Kang Z Y, Wang L, Guo S S et al. ASIE: An asynchronous SNN inference engine for AER events processing. ACM Journal on Emerging Technologies in Computing Systems , 2020, 16(4): 1–22. DOI: 10.1145/3404992.

[13]
Guo S S, Wang L, Wang S Q et al. A systolic SNN inference accelerator and its co-optimized software framework. In Proc. the 2019 on Great Lakes Symposium on VLSI, May 2019, pp.63–68. DOI: 10.1145/3299874.3317966.
[14]
Schrauwen B, Verstraeten D, Van Campenhout J. An overview of reservoir computing: Theory, applications and implementations. In Proc. the 15th European Symposium on Artificial Neural Networks, Apr. 2007, pp.471–482. https://www.esann.org/sites/default/files/proceedings/legacy/es2007-8.pdf, Sept. 2023.
[15]

Jithendar A, Daniel N, Tobi D, Shih-Chii L. Feature representations for neuromorphic audio spike streams. Frontiers in Neuroscience , 2018, 12:45–12:56. DOI: 10.3389/fnins.2018.00023.

[16]
Arnon A, Brian T, David B et al. A low power, fully event-based gesture recognition system. In Proc. the IEEE Conference on Computer Vision and Pattern Recognition, Jul. 2017, pp.7243–7252. DOI: 10.1109/CVPR.2017.781.
[17]
Kang Z Y, Wang S Y, Wang L et al. Application-specific network-on-chip design space exploration framework for neuromorphic processor. In Proc. the 17th ACM International Conference on Computing Frontiers, May 2020, pp.71–80. DOI: 10.1145/3387902.3392626.
[18]
Hu W M, Lu Z H, Jantsch A, Liu H Z. Power-efficient tree-based multicast support for networks-on-chip. In Proc. the 16th Asia and South Pacific Design Automation Conference, Jan. 2011, pp.363–368. DOI: 10.1109/ASPDAC.2011.5722214.
[19]
Li S M, Guo S S, Zhang L M et al. SNEAP: A fast and efficient toolchain for mapping large-scale spiking neural network onto NoC-based neuromorphic platform. In Proc. the 2020 on Great Lakes Symposium on VLSI, Sept. 2020, pp.9–14. DOI: 10.1145/3386263.3406900.
[20]

Bertsimas D, Tsitsiklis J. Simulated annealing. Statistical Science , 1993, 8(1): 10–15. DOI: 10.1214/ss/1177011077.

[21]
Kennedy J, Eberhart R. Particle swarm optimization. In Proc. International Conference on Neural Networks, Nov. 1995, pp.1942–1948. DOI: 10.1109/ICNN.1995.488968.
[22]
Moosavi S R, Rahmani A M, Liljeberg P et al. An efficient implementation of Hamiltonian path based multicast routing for 3D interconnection networks. In Proc. the 21st Iranian Conf. Electrical Engineering, May 2013. DOI: 10.1109/IranianCEE.2013.6599754.
[23]

Stimberg M, Brette R, Goodman D F. Brian 2, an intuitive and efficient neural simulator. eLife , 2019, 8:e47314. DOI: 10.7554/eLife.47314.

[24]
Beyeler M, Carlson K D, Chou T S, et al. CARLsim 3: A user-friendly and highly optimized library for the creation of neurobiologically detailed spiking neural networks. In Proc. the 2015 Int. Joint Conf. Neural Networks, Jul. 2015. DOI: 10.1109/IJCNN.2015.7280424.
Journal of Computer Science and Technology
Pages 1098-1112
Cite this article:
Kang Z-Y, Li S-M, Wang S-Y, et al. Path-Based Multicast Routing for Network-on-Chip of the Neuromorphic Processor. Journal of Computer Science and Technology, 2023, 38(5): 1098-1112. https://doi.org/10.1007/s11390-022-1232-8

298

Views

2

Crossref

2

Web of Science

2

Scopus

0

CSCD

Altmetrics

Received: 25 December 2020
Accepted: 03 March 2022
Published: 30 September 2023
© Institute of Computing Technology, Chinese Academy of Sciences 2023
Return