Event-based computation has recently gained increasing research interest for applications of vision recognition due to its intrinsic advantages on efficiency and speed. However, the existing event-based models for vision recognition are faced with several issues, such as large network complexity and expensive training cost. In this paper, we propose an improved multi-liquid state machine (M-LSM) method for high-performance vision recognition. Specifically, we introduce two methods, namely multi-state fusion and multi-liquid search, to optimize the liquid state machine (LSM). Multi-state fusion by sampling the liquid state at multiple timesteps could reserve richer spatiotemporal information. We adapt network architecture search (NAS) to find the potential optimal architecture of the multi-liquid state machine. We also train the M-LSM through an unsupervised learning rule spike-timing dependent plasticity (STDP). Our M-LSM is evaluated on two event-based datasets and demonstrates state-of-the-art recognition performance with superior advantages on network complexity and training cost.

Network-on-Chip (NoC) is widely adopted in neuromorphic processors to support communication between neurons in spiking neural networks (SNNs). However, SNNs generate enormous spiking packets due to the one-to-many traffic pattern. The spiking packets may cause communication pressure on NoC. We propose a path-based multicast routing method to alleviate the pressure. Firstly, all destination nodes of each source node on NoC are divided into several clusters. Secondly, multicast paths in the clusters are created based on the Hamiltonian path algorithm. The proposed routing can reduce the length of path and balance the communication load of each router. Lastly, we design a lightweight microarchitecture of NoC, which involves a customized multicast packet and a routing function. We use six datasets to verify the proposed multicast routing. Compared with unicast routing, the running time of path-based multicast routing achieves 5.1x speedup, and the number of hops and the maximum transmission latency of path-based multicast routing are reduced by 68.9% and 77.4%, respectively. The maximum length of path is reduced by 68.3% and 67.2% compared with the dual-path (DP) and multi-path (MP) multicast routing, respectively. Therefore, the proposed multicast routing has improved performance in terms of average latency and throughput compared with the DP or MP multicast routing.

Neuromorphic computing is considered to be the future of machine learning, and it provides a new way of cognitive computing. Inspired by the excellent performance of spiking neural networks (SNNs) on the fields of low-power consumption and parallel computing, many groups tried to simulate the SNN with the hardware platform. However, the efficiency of training SNNs with neuromorphic algorithms is not ideal enough. Facing this, Michael et al. proposed a method which can solve the problem with the help of DNN (deep neural network). With this method, we can easily convert a well-trained DNN into an SCNN (spiking convolutional neural network). So far, there is a little of work focusing on the hardware accelerating of SCNN. The motivation of this paper is to design an SNN processor to accelerate SNN inference for SNNs obtained by this DNN-to-SNN method. We propose SIES (Spiking Neural Network Inference Engine for SCNN Accelerating). It uses a systolic array to accomplish the task of membrane potential increments computation. It integrates an optional hardware module of max-pooling to reduce additional data moving between the host and the SIES. We also design a hardware data setup mechanism for the convolutional layer on the SIES with which we can minimize the time of input spikes preparing. We implement the SIES on FPGA XCVU440. The number of neurons it supports is up to 4000 while the synapses are 256000. The SIES can run with the working frequency of 200 MHz, and its peak performance is 1.5625 TOPS.