AI Chat Paper
Note: Please note that the following content is generated by AMiner AI. SciOpen does not take any responsibility related to this content.
{{lang === 'zh_CN' ? '文章概述' : 'Summary'}}
{{lang === 'en_US' ? '中' : 'Eng'}}
Chat more with AI
Article Link
Collect
Submit Manuscript
Show Outline
Outline
Show full outline
Hide outline
Outline
Show full outline
Hide outline
Research Article

Suppression of leakage current in carbon nanotube field-effect transistors

Lin XuChenguang QiuLian-mao Peng( )Zhiyong Zhang( )
Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China
Show Author Information

Graphical Abstract

Abstract

Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/µm and an on-current as high as about 2.1 mA/µm at a supply voltage of -1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

References

[1]
Y. Taur,; D. A. Buchanan,; W. Chen,; D. J. Frank,; K. E. Ismail,; S. H. Lo,; G. A. Sai-Halasz,; R. G. Viswanathan,; H. J. C. Wann,; S. J. Wind, et al. CMOS scaling into the nanometer regime. Proc. IEEE 1997, 85, 486-504.
[2]
D. A. Antoniadis,; I. Aberg,; C. N. Chleirigh,; O. M. Nayfeh,; A. Khakifirooz,; J. L. Hoyt, Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations. IBM J. Res. Dev. 2006, 50, 363-376.
[3]
M. Lundstrom, Moore’s law forever? Science 2003, 299, 210-211.
[4]
S. E. Thompson,; S. Parthasarathy, Moore’s law: The future of Si microelectronics. Mater. Today 2006, 9, 20-25.
[5]
G. Yeric, Moore’s Law at 50: Are we planning for retirement? In Proceedings of 2015 IEEE International Electron Devices Meeting (IEDM), Washington, USA, 2015, pp 1.
[6]
N. S. Kim,; T. Austin,; D. Baauw,; T. Mudge,; K. Flautner,; J. S. Hu,; M. J. Irwin,; M. Kandemir,; V. Narayanan, Leakage current: Moore’s law meets static power. Computer 2003, 36, 68-75.
[7]
R. Chau,; B. Doyle,; S. Datta,; J. Kavalieros,; K. Zhang, Integrated nanoelectronics for the future. Nat. Mater. 2007, 6, 810-812.
[8]
H. Iwai, End of the scaling theory and Moore’s law. In Proceedings of the 2016 16th International Workshop on Junction Technology (IWJT), Shanghai, China, 2016, pp 1-4.
[9]
L. M. Peng,; Z. Y. Zhang,; S. Wang, Carbon nanotube electronics: Recent advances. Mater. Today 2014, 17, 433-442.
[10]
Z. Y. Zhang,; S. Wang,; Z. X. Wang,; L. Ding,; T. Pei,; Z. D. Hu,; X. L. Liang,; Q. Chen,; Y. Li,; L. M. Peng, Almost perfectly symmetric SWCNT-based CMOS devices and scaling. ACS Nano 2009, 3, 3781-3787.
[11]
L. M. Peng,; Z. Y. Zhang,; C. G. Qiu, Carbon nanotube digital electronics. Nat. Electron. 2019, 2, 499-505.
[12]
A. Javey,; J. Guo,; Q. Wang,; M. Lundstrom,; H. J. Dai, Ballistic carbon nanotube field-effect transistors. Nature 2003, 424, 654-657.
[13]
C. S. Lee,; E. Pop,; A. D. Franklin,; W. Haensch,; H. S. P. Wong, A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—Part I: Intrinsic elements. IEEE Trans. Electron Dev. 2015, 62, 3061-3069.
[14]
L. Xu,; C. G. Qiu,; C. Y. Zhao,; Z. Y. Zhang,; L. M. Peng, Insight into ballisticity of room-temperature carrier transport in carbon nanotube field-effect transistors. IEEE Trans. Electron Dev. 2019, 66, 3535-3540.
[15]
A. D. Franklin, Nanomaterials in transistors: From high-performance to thin-film applications. Science 2015, 349, aab2750.
[16]
C. G. Qiu,; Z. Y. Zhang,; M. M. Xiao,; Y. J. Yang,; D. L. Zhong,; L. M. Peng, Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science 2017, 355, 271-276.
[17]
Z. Y. Zhang,; S. Wang,; L. Ding,; X. L. Liang,; T. Pei,; J. Shen,; H. L. Xu,; Q. Chen,; R. L. Cui,; Y. Li, et al. Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage. Nano Lett. 2008, 8, 3696-3701.
[18]
Z. Y. Zhang,; X. L. Liang,; S. Wang,; K. Yao,; Y. F. Hu,; Y. Z. Zhu,; Q. Chen,; W. W. Zhou,; Y. Li,; Y. G. Yao, et al. Doping-free fabrication of carbon nanotube based ballistic CMOS devices and circuits. Nano Lett. 2007, 7, 3603-3607.
[19]
J. Guo,; S. Datta,; M. Lundstrom, A numerical study of scaling issues for Schottky-barrier carbon nanotube transistors. IEEE Trans. Electron Dev. 2004, 51, 172-177.
[20]
S. Heinze,; J. Tersoff,; R. Martel,; V. Derycke,; J. Appenzeller,; P. Avouris, Carbon nanotubes as schottky barrier transistors. Phys. Rev. Lett. 2002, 89, 106801.
[21]
J. M. Larson,; J. P. Snyder, Overview and status of metal s/d Schottky-barrier MOSFET technology. IEEE Trans. Electron Dev. 2006, 53, 1048-1058.
[22]
J. Knoch,; M. Zhang,; J. Appenzeller,; S. Mantl, Physics of ultrathin- body silicon-on-insulator Schottky-barrier field-effect transistors. Appl. Phys. A 2007, 87, 351-357.
[23]
H. Ghoneim,; J. Knoch,; H. Riel,; D. Webb,; M. T. Björk,; S. Karg,; E. Lörtscher,; H. Schmid,; W. Riess, Suppression of ambipolar behavior in metallic source/drain metal-oxide-semiconductor field- effect transistors. Appl. Phys. Lett. 2009, 95, 213504.
[24]
C. G. Qiu,; Z. Y. Zhang,; D. L. Zhong,; J. Si,; Y. J. Yang,; L. M. Peng, Carbon nanotube feedback-gate field-effect transistor: Suppressing current leakage and increasing on/off ratio. ACS Nano 2015, 9, 969-977.
[25]
T. Srimani,; G. Hills,; X. Zhao,; D. Antoniadis,; J. A. del Alamo,; M. M. Shulaker, Asymmetric gating for reducing leakage current in carbon nanotube field-effect transistors. Appl. Phys. Lett. 2019, 115, 063107.
[26]
Y. M. Lin,; J. Appenzeller,; P. Avouris, Ambipolar-to-unipolar conversion of carbon nanotube transistors by gate structure engineering. Nano Lett. 2004, 4, 947-950.
[27]
M. Pourfath,; E. Ungersboeck,; A. Gehring,; B. H. Cheong,; W. Park,; H. Kosina,; S. Selberherr, Improving the ambipolar behavior of Schottky barrier carbon nanotube field effect transistors. In Proceedings of the 30th European Solid-State Circuits Conference, Leuven, Belgium, 2004, pp 429-432.
[28]
D. M. Caughey,; R. E. Thomas, Carrier mobilities in silicon empirically related to doping and field. Proc. IEEE 1967, 55, 2192-2193.
[29]
C. Nanmeni Bondja,; Z. S. Geng,; R. Granzner,; J. Pezoldt,; F. Schwierz, Simulation of 50-nm gate graphene nanoribbon transistors. Electronics 2016, 5, 3.
[30]
A. Betti,; G. Fiori,; G. Iannaccone, Drift velocity peak and negative differential mobility in high field transport in graphene nanoribbons explained by numerical simulations. Appl. Phys. Lett. 2011, 99, 242108.
[31]
D. Akinwande,; Y. Nishi,; H. S. P. Wong, An analytical derivation of the density of states, effective mass, and carrier density for achiral carbon nanotubes. IEEE Trans. Electron Dev. 2008, 55, 289-297.
[32]
J. L. Liang,; D. Akinwande,; H. S. P. Wong, Carrier density and quantum capacitance for semiconducting carbon nanotubes. J. Appl. Phys. 2008, 104, 064515.
[33]
H. S. P. Wong,; D. Akinwande, Carbon Nanotube and Graphene Device Physics; Cambridge University Press: Cambridge, 2011.
[34]
V. P. Trivedi,; J. G. Fossum, Nanoscale FD/SOI CMOS: Thick or thin BOX? IEEE Electron Dev. Lett. 2005, 26, 26-28.
[35]
T. Ernst,; C. Tinella,; C. Raynaud,; S. Cristoloveanu, Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: Optimization of the device architecture. Solid-State Electron. 2002, 46, 373-378.
[36]
J. Li,; A. Bansal,; K. Roy, Poly-Si thin-film transistors: An efficient and low-cost option for digital operation. IEEE Trans. Electron Dev. 2007, 54, 2918-2929.
[37]
S. Sahay,; M. J. Kumar, Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX. IEEE Trans. Electron Dev. 2015, 62, 3882-3886.
[38]
R. Chau,; S. Datta,; M. Doczy,; B. Doyle,; B. Jin,; J. Kavalieros,; A. Majumdar,; M. Metz,; M. Radosavljevic, Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 2005, 4, 153-158.
[39]
Q. Cao,; S. J. Han,; A. V. Penumatcha,; M. M. Frank,; G. S. Tulevski,; J. Tersoff,; W. E. Haensch, Origins and characteristics of the threshold voltage variability of quasiballistic single-walled carbon nanotube field-effect transistors. ACS Nano 2015, 9, 1936-1944.
[40]
E. Augendre,; R. Rooyackers,; M. de Potter de ten Broeck,; E. Kunnen,; S. Beckx,; G. Mannaert,; C. Vrancken,; V. Vassilev,; T. Chiarella,; M. Jurczak, et al. Thin L-shaped spacers for CMOS devices. In Proceedings of the 33rd Conference on European Solid-State Device Research, Estoril, Portugal, 2003, pp 219-222.
[41]
M. G. Ancona, Electron transport in graphene from a diffusion-drift perspective. IEEE Trans. Electron Dev. 2010, 57, 681-689.
[42]
S. Cristoloveanu,; J. Wan,; A. Zaslavsky, A review of sharp-switching devices for ultra-low power applications. IEEE J. Electron Dev. Soc. 2016, 4, 215-226.
[43]
C. G. Qiu,; F. Liu,; L. Xu,; B. Deng,; M. M. Xiao,; J. Si,; L. Lin,; Z. Y. Zhang,; J. Wang,; H. Guo, et al. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. Science 2018, 361, 387-392.
Nano Research
Pages 976-981
Cite this article:
Xu L, Qiu C, Peng L-m, et al. Suppression of leakage current in carbon nanotube field-effect transistors. Nano Research, 2021, 14(4): 976-981. https://doi.org/10.1007/s12274-020-3135-8
Topics:

1003

Views

31

Crossref

N/A

Web of Science

34

Scopus

0

CSCD

Altmetrics

Received: 30 August 2020
Revised: 09 September 2020
Accepted: 21 September 2020
Published: 01 December 2020
© Tsinghua University Press and Springer-Verlag GmbH Germany, part of Springer Nature
Return