Due to its remarkable electrical and optical capabilities, optoelectronic devices based on the semiconducting single-walled carbon nanotube (s-SWCNT) have been studied extensively in the last two decades. First, s-SWCNT is a direct bandgap semiconductor with a high infrared absorption coefficient and high electron/hole mobility. In addition, as a typical one-dimensional material, there is no lattice mismatch between s-SWCNT and any substrates. Another advantage is that the optoelectronic devices of s-SWCNT can be processed at low temperatures. s-SWCNT has intriguing potential and applications in solar cells, light-emitting diodes (LEDs), photodetectors, and three-dimensional (3D) optoelectronic integration. In recent years, along with the advancement of solution purification technology, the high-purity s-SWCNTs film has laid the foundation for constructing large-area, homogenous, and high-performance optoelectronic devices. In this review, optoelectronic devices based on s-SWCNTs film and related topics are reviewed, including the preparation of high purity s-SWCNTs film, the progress of photodetectors based on the s-SWCNTs film, and challenges of s-SWCNTs film photodetectors.

Thanks to its single-atomic-layer structure, high carrier transport, and low power dissipation, carbon nanotube electronics is a leading candidate towards beyond-silicon technologies. Its low temperature fabrication processes enable three-dimensional (3D) integration with logic and memory (static random access memory (SRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.) to realize efficient near-memory computing. Importantly, carbon nanotube transistors require good thermal stability up to 400 °C processing temperature to be compatible with back-end-of-line (BEOL) process, which has not been previously addressed. In this work, we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity, where AlN was employed as electrostatic doping layer. The gate stack and passivation layer were optimized to realize high-quality interfaces. Specifically, we demonstrate 1-bit carbon nanotube full adders working under 250 °C with rail-to-rail outputs.

Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/µm and an on-current as high as about 2.1 mA/µm at a supply voltage of -1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

A small bandgap and light carrier effective mass (m₀) lead to obvious ambipolar transport behavior in carbon nanotube (CNT) field-effect transistors (FETs), including a high off-state current and severe degradation of the subthreshold swing (SS) with increasing drain bias voltage. We demonstrate a drain-engineered method to cope with this common problem in CNT-film FETs with a sub-μm channel length, i.e., suppressing the ambipolar behavior while maintaining high on-state performance by adopting a feedback gate (FBG) structure to extend the drain region from the CNT/metal contact to the proximate CNT channels to suppress the tunneling current. Sub-400-nm-channel-length FETs with a FBG structure statistically present a high on/off ratio of up to 10⁴ and a sub-200 mV/dec SS under a high drain bias of up to -2 V while maintaining a high on-state current of 0.2 mA/μm or a peak transconductance of 0.2 mS/μm. By lowering the supply voltage to 1.5 V, FBG CNT-film FETs can meet the requirement of standard-performance ultra large scale integrated circuits (ULSICs). Therefore, the introduction of the drain engineering structure enables applications of CNT-film-based FETs in ULSICs and could also be widely extended to other small-bandgap semiconductor-based FETs for an improvement in their off-state property.

Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.

We have fabricated top-gated ambipolar field-effect transistors (FETs) based on solution-derived carbon nanotube (CNT) network films, and then constructed inverters and ring oscillators (ROs) that can work under supply voltages as low as 0.2 V owing to the high uniformity of the devices. Significant improvements were achieved in the performance of these CNT-based ambipolar FETs and CMOS-like circuits by scaling down the gate length of the CNT FETs and optimizing the device structure and RO layout. In particular, the optimized five-stage RO is shown to present a record high oscillation frequency of up to 17.4 MHz with a propagation time of 5.6 ns at a 12-V working voltage. The CNT film-based ROs were used as carrier-wave generators in radio-frequency systems to demonstrate a complete signal transmission process. These results suggest that CNT thin film-based FETs and integrated circuits may soon find their way to radio-frequency applications with a frequency band of 13.56 MHz.

Sub-micron color sensors are developed, using carbon nanotubes (CNTs). The color sensor consists of an array of two photodiodes with different spectral responses, fabricated using controlled electric peeling-off and doping-free techniques on a single semiconducting double-wall CNT. The CNT photodiodes exhibit intrinsic broad spectral responses from 640 to 2, 100 nm, large linear dynamic ranges of over 60 dB, and sub-micron pixel size. This method explores the unique properties of multi-wall CNTs, and may be readily used for large-scale fabrication of high performance color sensor arrays, when arrays of parallel multi-wall CNTs become available.

A novel three-dimensional device structure for a carbon nanotube (CNT) fin field-effect transistor (FinFET) is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product (EDP). Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage (V_th = 1/3V_dd). A suitable improvement in V_th can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage (V_dd = 0.4 V), suggesting great potential for CNT FinFET-based integrated circuits.

Realizing low contact resistance between graphene and metal electrodes remains a well-known challenge for building high-performance graphene devices. In this work, we attempt to reduce the contact resistance in graphene transistors and further explore the resistance limit between graphene and metal contacts. The Pd/graphene contact resistance at room temperature is reduced below the 100 Ω·μm level both on mechanically exfoliated and chemical-vapor-deposition graphene by adopting high-purity palladium and high-quality graphene and controlling the fabrication process to not contaminate the interface. After excluding the parasitic series resistances from the measurement system and electrodes, the retrieved contact resistance is shown to be systematically and statistically less than 100 Ω·μm, with a minimum value of 69 Ω·μm, which is very close to the theoretical limit. Furthermore, the contact resistance shows no clear dependence on temperature in the range of 77–300 K; this is attributed to the saturation of carrier injection efficiency between graphene and Pd owing to the high quality of the graphene samples used, which have a sufficiently long carrier mean-free-path.

The speed of frequency response of all published carbon nanotube (CNT) integrated circuits (ICs) is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor (FET) based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 μs. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive (RC) delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs.