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Open Access

Optimization and Evaluation of Sputtering Barrier/Seed Layer in Through Silicon Via for 3-D Integration

Tiwei Wei, Jian Cai( ), Qian Wang, Yang Hu, Lu Wang, Ziyu Liu, Zijian Wu
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Institute of Microelectronics and Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, China
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Abstract

The barrier/seed layer is a key issue in Through Silicon Via (TSV) technology for 3-D integration. Sputtering is an important deposition method for via metallization in semiconductor process. However, due to the limitation of sputtering and a "scallop" profile inside vias, poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper, the effects of several sputter parameters (DC power, Ar pressure, deposition time, and substrate temperature) on thin film coverage for TSV applications are investigated. Robust TSVs with aspect ratio 5∶1 were obtained with optimized magnetron sputter parameters. In addition, the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.

Keywords

barrier/seed layerThrough Silicon Via (TSV)sputteringoptimization

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Tsinghua Science and Technology
Volume 19 Issue 2,
April 2014
Pages 150-160
DOI: 10.1109/TST.2014.6787368
Cite this article:
Wei T, Cai J, Wang Q, et al. Optimization and Evaluation of Sputtering Barrier/Seed Layer in Through Silicon Via for 3-D Integration. Tsinghua Science and Technology, 2014, 19(2): 150-160. https://doi.org/10.1109/TST.2014.6787368

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Received: 07 March 2014
Accepted: 16 March 2014
Published: 15 April 2014
© The author(s) 2014
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