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Open Access Issue
Thermal Resistance Simulation for CoF Packages
Tsinghua Science and Technology 2015, 20(3): 277-284
Published: 01 June 2015
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Chip-on-Film (CoF) is a packaging technology that mounts Integrated Circuits (IC) chips directly on a flexible substrate surface. As both power and the number of pins in such packages increase, thermal conditions become more important. In this paper, the thermal resistance of CoF packages is studied using Ansys software to perform finite-element analysis. Because of circuit complexity, two equivalent methods—a length-weighted method and an image-recognition method—are proposed in place of an accurate model to get equivalent thermal conductivity of CoF package devices. In our experiments, the simulated value of thermal resistance based on the length-weighted method was 1.653 K/W, and the value based on the image-recognition method was 1.911 K/W. The real thermal resistance value of the CoF package device is 1.812 K/W. So the error between the real value measured by a tester and the simulated value based on the length-weighted method is 8.8%, and the error between the real value and the simulated value based on the image-recognition method is 5.5%. Hence, both methods can provide effective simulation results, and the image-recognition method is more accurate. In addition, we optimized the CoF package structure. From the simulation results, the drop in thermal resistance after the optimization is obvious.

Open Access Issue
Optimization and Evaluation of Sputtering Barrier/Seed Layer in Through Silicon Via for 3-D Integration
Tsinghua Science and Technology 2014, 19(2): 150-160
Published: 15 April 2014
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Downloads:93

The barrier/seed layer is a key issue in Through Silicon Via (TSV) technology for 3-D integration. Sputtering is an important deposition method for via metallization in semiconductor process. However, due to the limitation of sputtering and a "scallop" profile inside vias, poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper, the effects of several sputter parameters (DC power, Ar pressure, deposition time, and substrate temperature) on thin film coverage for TSV applications are investigated. Robust TSVs with aspect ratio 5∶1 were obtained with optimized magnetron sputter parameters. In addition, the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.

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