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Open Access

Thermal Resistance Simulation for CoF Packages

Chuan ChenQian WangXiaotian MengLin TanJian WangChengqiang CuiJian Cai( )
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
AKM Electronics Technology (Suzhou) Company Ltd., Suzhou 215000, China
Institute of Microelectronics and Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, China
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Abstract

Chip-on-Film (CoF) is a packaging technology that mounts Integrated Circuits (IC) chips directly on a flexible substrate surface. As both power and the number of pins in such packages increase, thermal conditions become more important. In this paper, the thermal resistance of CoF packages is studied using Ansys software to perform finite-element analysis. Because of circuit complexity, two equivalent methods—a length-weighted method and an image-recognition method—are proposed in place of an accurate model to get equivalent thermal conductivity of CoF package devices. In our experiments, the simulated value of thermal resistance based on the length-weighted method was 1.653 K/W, and the value based on the image-recognition method was 1.911 K/W. The real thermal resistance value of the CoF package device is 1.812 K/W. So the error between the real value measured by a tester and the simulated value based on the length-weighted method is 8.8%, and the error between the real value and the simulated value based on the image-recognition method is 5.5%. Hence, both methods can provide effective simulation results, and the image-recognition method is more accurate. In addition, we optimized the CoF package structure. From the simulation results, the drop in thermal resistance after the optimization is obvious.

References

[1]
Zhang, H. Cai, J. Wang, Q. Wang, T. and Wang, S. Development of a BGA package based on Si interposer with through silicon via, Tsinghua Science and Technology, vol. 16, no. 4, pp. 1002-1008, 2011.
[2]
Wei, T. Cai, J. Wang, Q. Hu, Y. Wang L., Liu, Z. and Wu, Z. Optimization and evaluation of sputtering barrier/seed layer in through silicon via for 3-D integration, Tsinghua Science and Technology, vol. 19, no. 2, pp. 150-160, 2014.
[3]
Kim, Y. G. Folded stacked package development, presented at the 52th Electronic Components and Technology Conference, San Diego, USA, 2002.
[4]
Barton, J. Majeed, B. Dwane, K. Delaney, K. Bellis, S. Rodgers, K. and O’Mathuna, S. C. Development and characterisation of ultrathin autonomous modules for ambient system applications using 3D packaging techniques, in Electronic Components and Technology Conference Proceedings, 2004, pp. 635-641.
[5]
Liu, D. S. Yeh, S. S. Kao, C. T. Shen, H. C. Shen, G. S. and Liu, H. H. Optimization of bonding force, sinking value, and potting gap size in COF inner lead bonding process, IEEE Trans. Adv. Packag., vol. 32, no. 3, pp. 593-601, 2009.
[6]
Lau, J. H. Handbook of Tape Automated Bonding. New York, USA: Van Nostrand Reinhold, 1992.
[7]
Ramadoss, R. Lee, S. Lee, Y. C. Bright, V. M. and Gupta, K. C. Flexible polyimide film based high isolation RF MEMS switches fabricated using printed circuit processing techniques, in Proc. 18th IEEE Int. Conf. Micro Electro Mechanical Systems, Miami, FL, USA, 2005, pp. 179-182.
[8]
Tsai, J. Y. Chang, C. W. Shieh, Y. C. Hu, Y. C. and Kao, C. R. Controlling the microstructure from the gold-tin reaction, J. Electron. Mater., vol. 34, no. 2, pp. 182-187, 2005.
[9]
Liu, D. Yeh, S. Lu, C. Chang, C. Hung, C. Liu, A. and Liu, H. Thermal performance study of next generation fine-pitch chip-on-film (COF) packages—A numerical study, in Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International, IEEE, 2011, pp. 273-275.
[10]
EIA J S. JESD51-1, Integrated Circuits Thermal Measurement Method—Electrical Test Method (Single Semiconductor Device), 1995.
[11]
Kandasamy R. and Mujumdar, A. S. Interface thermal characteristic of flip chip packages—A numerical study, Applied Thermal Engineering, vol. 29, no. 5, pp. 822-829, 2009.
[12]
Gurrum, S. P. Suman, S. K. Joshi, Y. K. and Fedorov, A. G. Thermal issues in next-generation integrated circuit, IEEE Trans. Device Mater. Rel., vol. 4, no. 4, pp. 709-714, 2004.
[13]
Bivragh, M. Kelley, M. Van Sinte Jans, J. B. Indrajit, P. Slattery, O. Barton, J. O’Mathuna, S. C. O’Flynn, B. and Malshe, A. P. Thermo-mechanical modelling and thermal performance characterisation of a 3D folded flex module, presented at the 56th Electronic Components and Technology Conference, San Diego, USA, 2006.
[14]
Chen, W. Cheng, H. and Shen, H. An effective methodology for thermal characterization of electronic packaging, Components and Packaging Technologies, IEEE Transactions on, vol. 26, no. 1, pp. 222-232, 2003.
[15]
Lee T. T. and Mahalingam, M. Thermal limits of flip chip package-experimentally validated, CFD supported case studies, Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on, vol. 20, no. 1, pp. 94-103, 1997.
[16]
Ellison, G. N. Thermal Computations for Electronic Equipment. Malabar, FL, USA: R. E. Krieger Publishing Company, 1989.
Tsinghua Science and Technology
Pages 277-284
Cite this article:
Chen C, Wang Q, Meng X, et al. Thermal Resistance Simulation for CoF Packages. Tsinghua Science and Technology, 2015, 20(3): 277-284. https://doi.org/10.1109/TST.2015.7128940

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Received: 20 March 2015
Accepted: 20 April 2015
Published: 01 June 2015
© The authors 2015
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