In this work, we consider an Unmanned Aerial Vehicle (UAV)-aided covert transmission network, which adopts the uplink transmission of Communication Nodes (CNs) as a cover to facilitate covert transmission to a Primary Communication Node (PCN). Specifically, all nodes transmit to the UAV exploiting uplink non-Orthogonal Multiple Access (NOMA), while the UAV performs covert transmission to the PCN at the same frequency. To minimize the average age of covert information, we formulate a joint optimization problem of UAV trajectory and power allocation designing subject to multi-dimensional constraints including covertness demand, communication quality requirement, maximum flying speed, and the maximum available resources. To address this problem, we embed Signomial Programming (SP) into Deep Reinforcement Learning (DRL) and propose a DRL framework capable of handling the constrained Markov decision processes, named SP embedded Soft Actor-Critic (SSAC). By adopting SSAC, we achieve the joint optimization of UAV trajectory and power allocation. Our simulations show the optimized UAV trajectory and verify the superiority of SSAC compared with various existing baseline schemes. The results of this study suggest that by maintaining appropriate distances from both the PCN and CNs, one can effectively enhance the performance of covert communication by reducing the detection probability of the CNs.

When implementing helicopter $\mathrm{-}$satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter $\mathrm{-}$satellite channel model and the Forward Error Control (FEC) coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid (CH) Low-Density Parity-Check (LDPC) codes are designed to mitigate the periodical blockage over the helicopter $\mathrm{-}$satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC (QC-LDPC) code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter $\mathrm{-}$satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQC-LDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary Phase-Shift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.

In this study, a class of Generalized Low-Density Parity-Check (GLDPC) codes is designed for data transmission over a Partial-Band Jamming (PBJ) environment. The GLDPC codes are constructed by replacing parity-check code constraints with those of nonsystematic Bose-Chaudhuri-Hocquenghem (BCH), referred to as Low-Density Parity-Check (LDPC)-BCH codes. The rate of an LDPC-BCH code is adjusted by selecting the transmission length of the nonsystematic BCH code, and a low-complexity decoding algorithm based on message-passing is presented that employs A Posteriori Probability (APP) fast BCH transform for decoding the BCH check nodes at each decoding iteration. Simulation results show that the LDPC-BCH codes with a code rate of 1/8.5 have a bit error rate performance of 1 $\mathrm{\times }$10 ${}^{\mathrm{-}6}$ at signal-noise-ratios of $\mathrm{-}$6.97 dB, $\mathrm{-}$4.63 dB, and 2.48 dB when the fractions of the band jammed are 30%, 50%, and 70%, respectively.