In recent years, Approximate Computing Circuits (ACCs) have been widely used in applications with intrinsic tolerance to errors. With the increased availability of approximate computing circuit approaches, reliability analysis methods for assessing their fault vulnerability have become highly necessary. In this study, two accurate reliability evaluation methods for approximate computing circuits are proposed. The reliability of approximate computing circuits is calculated on the basis of the iterative Probabilistic Transfer Matrix (PTM) model. During the calculation, the correlation coefficients are derived and combined to deal with the correlation problem caused by fanout reconvergence. The accuracy and scalability of the two methods are verified using three sets of approximate computing circuit instances and more circuits in EvoApprox8b, which is an approximate computing circuit open source library. Experimental results show that relative to the Monte Carlo simulation, the two methods achieve average error rates of 0.46% and 1.29% and time overheads of 0.002% and 0.1%. Different from the existing approaches to reliability estimation for approximate computing circuits based on the original PTM model, the proposed methods reduce the space overheads by nearly 50% and achieve time overheads of 1.78% and 2.19%.

Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.