Molybdenum disulfide (MoS₂), one of transition metal dichalcogenides, is a promising semiconductor material for electronic or optoelectronic devices due to its favorably electronic properties. However, in metal-oxide semiconductor field-effect transistor (MOSFET) structures using MoS₂, electrical performances such as mobility and subthreshold swing are suppressed by the interface trap density between the channel and dielectric layers. Moreover, the electrical stability of such structures is compromised due to interface traps and that can be analyzed such as current hysteresis and transient characteristics. Here, we demonstrate MoS₂ heterojunction field-effect transistors (HFET) by applying MoS₂/p⁺-Si heterojunctions and achieve high performance characteristics, including a mobility of 636.19 cm²/(V∙s), a subthreshold swing of 67.4 mV/dec, minimal hysteresis of 0.05 V, and minimized transient characteristics. However, the HFET devices with varying the channel length demonstrated degradation of electrical performance with increasing the overlap area of the channel and dielectric layers. These results regarding MoS₂/p⁺-Si HFETs resulted in the structural optimization of high-performance electronic devices for practical applications.

Two-dimensional (2D) crystals have a multitude of forms, including semi-metals, semiconductors, and insulators, which are ideal for assembling isolated 2D atomic materials to create van der Waals (vdW) heterostructures. Recently, artificially-stacked materials have been considered promising candidates for nanoelectronic and optoelectronic applications. In this study, we report the vertical integration of layered structures for the fabrication of prototype non-volatile memory devices. A semiconducting-tungsten-disulfide-channel-based memory device is created by sandwiching high-density-of-states multi-layered graphene as a carrier-confining layer between tunnel barriers of hexagonal boron nitride (hBN) and silicon dioxide. The results reveal that a memory window of up to 20 V is opened, leading to a high current ratio (> 10³) between programming and erasing states. The proposed design combination produced layered materials that allow devices to attain perfect retention at 13% charge loss after 10 years, offering new possibilities for the integration of transparent, flexible electronic systems.